Pi 4 questions

[Mikael]

I'm an embedded systems engineer myself and it's a fun game trying to guess what the next Pi will be (NOTE: Not making wish lists! ). I see people suggesting big-little type setups, but I don't really think that makes any sense. For a cell phone? Yes. For a Pi? Not really. Big-little type setups add complexity to both hardware and software and it also makes the system less predictable in terms of performance. In my view, it makes more sense to optimize the Pi for sustained performance. My own personal guess is that the Pi 4 will keep using a four core cluster of identical cores. I am also guessing that one goal with the Pi 4 is to reduce the power consumption, which has kind of ballooned with Pi 3 and Pi 3 B+. Being able to sustain a decent load with passive cooling without hitting thermal throttling is of course desirable.

Is 28 nm is enough of an improvement to provide both a worthwhile power consumption reduction while also providing a sizable performance increase? Not sure, to be honest. I get the impression that the Pi 4 is going to feature a pretty hefty performance increase, so maybe the Foundation is able to pull off a 16/14/12 nm class design while keeping it all within the extremely tight budget constraints?

[jamesh]

The main thing I'd like to see in a Pi4 or any of it's successors is a constant rate clock to the baud rate divider for any and all uarts. It's not much to ask.

Roger

Yes, it's a pain, but actually quite a big ask, requiring major silicon changes, and that sort of thing starts at a good chunk of $1M.

[hippy]

The main thing I'd like to see in a Pi4 or any of it's successors is a constant rate clock to the baud rate divider for any and all uarts. It's not much to ask.

Roger

Yes, it's a pain, but actually quite a big ask, requiring major silicon changes, and that sort of thing starts at a good chunk of $1M.

In the grand scheme of things that's not a lot for a company which had a £61 million turnover with £24 million profit ($31m) up to the end of 2017, and has likely only added to that in the last year.

I would have expected swapping the mini-UART peripheral cell for a full-UART cell would have comparable costs with creating the BCM2836 and BCM2837 multi-core variants but I'll admit I'm not knowledgeable about silicon spin costs.

More intriguing is the way you present it, as I read it, that, it would be nice to have, but too expensive, so not going to happen. I would have thought that, unless the Pi 4 is going to be using the exact same peripheral cell block, that would simply be a change of cell which would be a part and parcel of other changes, its cost disappearing amongst the costs of producing the Pi 4 itself. Maybe I'm misreading that.

[ejolson]

I see people suggesting big-little type setups, but I don't really think that makes any sense.

The Spectre side-channel attacks rely on speculative out-of-order execution of untrusted code.

Since the unfortunate desire to run JavaScript in a web browser is unlikely to go away, it could be useful to have some in-order cores on which to run the untrusted code. These are available in the little part of a big.LITTLE CPU. As a result there no need to slow the out-of-order cores down with inefficient cache-flushing and trampoline-style Spectre mitigations.

The questions I have are, why haven't we seen this kind of approach being taken for running untrusted code securely in a web browser on an ARM-based desktop? Is this something for the Pi 4?

[Mikael]

The Spectre side-channel attacks rely on speculative out-of-order execution of untrusted code.

Since the unfortunate desire to run JavaScript in a web browser is unlikely to go away, it could be useful to have some in-order cores on which to run the untrusted code. These are available in the little part of a big.LITTLE CPU. As a result there no need to slow the out-of-order cores down with inefficient cache-flushing and trampoline-style Spectre mitigations.

The questions I have are, why haven't we seen this kind of approach being taken for running untrusted code securely in a web browser on an ARM-based desktop? Is this something for the Pi 4?

That's an interesting work-around, but a pretty heavy handed one. My guess: This issue will be pretty much ignored for the Pi 4 and the RPF will choose whatever ARM core (be it A5X or A7X) that fulfills the requirements without breaking the budgets (including transistor and power budgets).

[spock]

but why would a big.LITTLE CPU be advantageous for spectre mitigation?

in my understanding out-of-order execution simply could be disabled in a big core and then power consumption also would go down and be comparable to a little core? so better put in 8 big cores and disable out-of-order execution if necessary!

[W. H. Heydt]

I realize that the x86 world has gone core crazy (look up Intel and AMDs latest offerings), but with the other resource constraints on the Pi, I really doubt that anything more than 4 cores makes any sense. Only if memory were increased by nearly an order of magnitude, and I/O went not to USB 3.0 (5Gb/s), but to at least USB 3.1 (10Gb/s) could more than four cores be reasonably supported.

[ejolson]

but why would a big.LITTLE CPU be advantageous for spectre mitigation?

in my understanding out-of-order execution simply could be disabled in a big core and then power consumption also would go down and be comparable to a little core? so better put in 8 big cores and disable out-of-order execution if necessary!

A big core with features disabled (even if possible) still spends the transistor budget for whatever fabrication process is being used. In particular, an A57 core takes about 5 times as much space on die as an A53 core.

Since big.LITTLE is an existing technology, why not make efficient desktop use of it? Could this be something for the Pi 4?

[Gavinmc42]

I really doubt that anything more than 4 cores makes any sense.

Do the 48 ALU's in the 12 QPU's count as cores?
The 2 vector cpu's in the VC4 that control them.
Scaler cpu's as well?
Can an ALU be called a CPU?

Exactly how many ALU's that can be coded do we have?
Will we get more or faster versions of the same?

Er, how many VPU/QPUs does the VC5 have?
Will the Pi4 get VC4 or VC5 or something else?

Important questions for stuff like OpenCL.
Did that Khronos OpenVX ever get ported to Pi3B+? Whoops off track.

[W. H. Heydt]

I really doubt that anything more than 4 cores makes any sense.

Do the 48 ALU's in the 12 QPU's count as cores?
The 2 vector cpu's in the VC4 that control them.
Scaler cpu's as well?
Can an ALU be called a CPU?

I wouldn't count them any more than I would count all the various "cores" one find in a modern graphics card from AMD or nVidia.

[jamesh]

I really doubt that anything more than 4 cores makes any sense.

Do the 48 ALU's in the 12 QPU's count as cores?
The 2 vector cpu's in the VC4 that control them.
Scaler cpu's as well?
Can an ALU be called a CPU?

Exactly how many ALU's that can be coded do we have?
Will we get more or faster versions of the same?

Er, how many VPU/xQPUs does the VC5 have?
Will the Pi4 get VC4 or VC5 or something else?

Important questions for stuff like OpenCL.
Did that Khronos OpenVX ever get ported to Pi3B+? Whoops off track.

All your posts are off track in one way or another, no need to state it.

[Gavinmc42]

All your posts are off track in one way or another, no need to state it.

Shucks, thanks
Yep, wife says I ramble and don't get to the point.

Not my fault, you guys make me think and start me going off in tangents.
I blame Eben, all his fault for making the Pi
Since 2012 I have had to learn so much there seems to be leakage.
Plus I'm getting old and forget what I write, lucky Google can find me again.

[W. H. Heydt]

All your posts are off track in one way or another, no need to state it.

Shucks, thanks
Yep, wife says I ramble and don't get to the point.

Not my fault, you guys make me think and start me going off in tangents.
I blame Eben, all his fault for making the Pi
Since 2012 I have had to learn so much there seems to be leakage.
Plus I'm getting old and forget what I write, lucky Google can find me again.

Congrats. Well handled. (Plus...I resemble that remark.)

But, really, the issue in dispute is at least as old as usenet. Threads drift.

[Yammers]

Surgestions for Raspberry Pi 4

What I would like to see as i am intrested in using an SBC for a Nas like the Helios 4 is a Server Bord variation allowing for 4/6 sata ports and transcoding.

Also i think that allowing 10inc displays to be added and nvme or m.2. drives to me added as well.

I would like it to have on off button as standard. I know they want to keep the cost about the same but maybe they could for a future model make the single board computerr the size of say a Original Iphone or samsung s8 size, it could then pack a wollop.

[jamesh]

Surgestions for Raspberry Pi 4

What I would like to see as i am intrested in using an SBC for a Nas like the Helios 4 is a Server Bord variation allowing for 4/6 sata ports and transcoding.

Also i think that allowing 10inc displays to be added and nvme or m.2. drives to me added as well.

I would like it to have on off button as standard. I know they want to keep the cost about the xsame but maybe they could for a future model make the single board computerr the size of say a Original Iphone or samsung s8 size, it could then pack a wollop.

Nah, miles off.



Or is it......

[DarkPlatinum]

Nah, miles off.



Or is it......

He is telling us something, what is he saying

[W. H. Heydt]

I would like it to have on off button as standard.

Funny thing about that.... For a while (until WD shut it down), WD Labs made Pi accessories. One of them was a CM carrier board. They actually set the power up sufficiently to handle a CM3, when those came out. The normal purpose of the board was to provide a CM/CM3 with a SATA connection. The packaging, with a plastic frame (original versions of which came with magnets at the corners...very handy) is quite good.

There were...some design flaws. The first being, 2 USB ports and no Ethernet. The second being that the early boards work like a champ booting an MSD directly with a CM3L (once one sets the OTP bit). The problem is that later boards won't work that way. I think they changed out something in the USB hub and/or SATA bridge and later boards don't work correctly. (And...FYI...as soon as I get my hands on a CM3L+ I will be testing that to see if there are any changes that make late model WD SATA Adapter carriers work.)

One of the other features of the SATA Adapter board is...a real, physical power button.

Now to drag this back to the present... Even if WD Labs were still in operation and making Pi stuff, I don't think the SATA Adapter will work if we get a CM4L. The reason being that one hopes the Pi 4 SoC will have USB 3 and I don't know what effect that will have on the required pinouts to the carrier.

In a fairly recent video interview with Dr. Upton I saw, he said that the only times that the RPF/RPT gets into making stuff other than Pis is when either the market fails to do so or the items on the market aren't what they should be. I think the WD SATA Adapter falls into both categories. On the one hand, the lack of network connections and on the other, you can't get them any more.

So... What I'd like to see some time down the road (i.e. *after* the Pi4B and *after* there are CM4/CM4L modules available) would be a New, Improved, designed by the RPT SATA Adapter 4 carrier board. It could even include the power switch.