Hello,
can anybody help me to findout how to make gpio as chipselect. as there is 2 chip select provided by the pi. i need a third one .
so how can i done it?
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monisha.om
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DougieLawson
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Re: How to make gpio as chipselect
Any language using left-hand whitespace for syntax is ridiculous
Any DMs sent on Twitter will be answered next month.
Fake doctors - are all on my foes list.
Any requirement to use a crystal ball or mind reading will result in me ignoring your question.
Any DMs sent on Twitter will be answered next month.
Fake doctors - are all on my foes list.
Any requirement to use a crystal ball or mind reading will result in me ignoring your question.
Re: How to make gpio as chipselect
I used to use the dtoverlay command I don’t know if it’s still current though.
Name: spi1-3cs
Info: Enables spi1 with three chip select (CS) lines and associated spidev
dev nodes. The gpio pin numbers for the CS lines and spidev device node
creation are configurable.
N.B.: spi1 is only accessible on devices with a 40pin header, eg:
A+, B+, Zero and PI2 B; as well as the Compute Module.
Load: dtoverlay=spi1-3cs,<param>=<val>
Params: cs0_pin GPIO pin for CS0 (default 18 - BCM SPI1_CE0).
cs1_pin GPIO pin for CS1 (default 17 - BCM SPI1_CE1).
cs2_pin GPIO pin for CS2 (default 16 - BCM SPI1_CE2).
cs0_spidev Set to 'disabled' to stop the creation of a
userspace device node /dev/spidev1.0 (default
is 'okay' or enabled).
cs1_spidev Set to 'disabled' to stop the creation of a
userspace device node /dev/spidev1.1 (default
is 'okay' or enabled).
cs2_spidev Set to 'disabled' to stop the creation of a
userspace device node /dev/spidev1.2 (default
is 'okay' or enabled).
Name: spi1-3cs
Info: Enables spi1 with three chip select (CS) lines and associated spidev
dev nodes. The gpio pin numbers for the CS lines and spidev device node
creation are configurable.
N.B.: spi1 is only accessible on devices with a 40pin header, eg:
A+, B+, Zero and PI2 B; as well as the Compute Module.
Load: dtoverlay=spi1-3cs,<param>=<val>
Params: cs0_pin GPIO pin for CS0 (default 18 - BCM SPI1_CE0).
cs1_pin GPIO pin for CS1 (default 17 - BCM SPI1_CE1).
cs2_pin GPIO pin for CS2 (default 16 - BCM SPI1_CE2).
cs0_spidev Set to 'disabled' to stop the creation of a
userspace device node /dev/spidev1.0 (default
is 'okay' or enabled).
cs1_spidev Set to 'disabled' to stop the creation of a
userspace device node /dev/spidev1.1 (default
is 'okay' or enabled).
cs2_spidev Set to 'disabled' to stop the creation of a
userspace device node /dev/spidev1.2 (default
is 'okay' or enabled).
You can make a real CPU in a FPGA, but you can’t make a real FPGA in a CPU.
Re: How to make gpio as chipselect
I don't know whether the Xilinx spi driver supports that or not - I'd guess not - but you do not need to, anyway. Instead, you can rewire the SPI1 interface inside the FPGA and use the spi driver in it's standard way. On the FPGA-side, you'd have to
source: 192.168.1.1
- reconfigure the ZYNQ-IP to map SPI1 to EMIO
enable one or two additional SlaveSelects on SPI1
disable UART1
route the new SPI1 connections on the IP to red_pitaya_top and tie them to FIXED_IO_mio[8-12] - that's where UART1 and SPI1 were previously
make sure that the external drivers for the MIO pins are configured correctly - since the devices on them are now disabled, they will no longer automatically inherit their configuration
source: 192.168.1.1