WARNING GEEKY VHDL/Verilog/Sim type stuff, move along if not interested
John Beetem said:
I do a lot of FPGA design, primarily for Xilinx Spartan-IIe/3A. Xilinx and others provide free software tools (WebPack) for the smaller parts, but they only run on x86 PCs. At least they now have GNU/Linux versions available.
Xilinx and other vendors have always been openly hostile towards open source software, not wanting to publish the details of their architecture and programming stream. It's very sad, as IMO they would have made vastly more money over the decades if they had.
I think we are going to have to agree to disagree on stuff there, but agree on a lot as well .
Personally I'd prefer to use simulation with a LOT of testing prior to hitting the synth button. That's not just because of my ASIC background but I've seen the pain and the number of iterations that a lot of people have gone through when a simple TestBench could have shown the issues. I've done a lot of stuff that has required software to get involved, getting an entire sim together with at least register accesses to simulate software clears up a lot of issues. That means when you get to present something to the software eng the likelyhood is that the system will work pretty quickly. I think the last block went through without any iteration and the previous one had one bug in the design (but that was down to the classic who will guard the guards problem).
Simulation/Verification has come a little way but with all things you have to take/be given the time to do the job. Philosophically you have to do the work twice, once for the actual block and again for the 'inverse' to test it. Getting PMs who have NO IDEA ABOUT THE FLOW to understand this can be frustrating at times.
You may wish to look at System Verilog, there are things like Formal Techniques in there I believe. Sadly I can't confirm, I was due to go on a course but had to give it up as a PM wanted something desperately so I had to fore go the course.
As to VHDL/Verilog, well it's like editors and stuff, whatever works for you . I personally prefer VHDL over Verilog for things such as types, enumerated types, records etc (SV now has that stuff ). I will have to see how hard it is to generate a tree in Verilog cleanly without records, but hey if all things work out I'll be writing a lot in Verilog soon !
As to writing code for synthesis, well I was always taught to envision the logic you want and then code for it. Things like resource sharing, pipelining etc.
However it is easier in an ASIC flow, you do actually get to see the gates at synth. FPGA yes you are VERY MUCH hostage to fortune withI revision levels of the tools. I have almost been driven to tears by the tools you speak of. I have seen them generate incorrect logic which is so VERY VERY scary. This is something I don't think I ever saw in the ASIC flows (bad cells, but not bad synthesis).
Always nice to chat with other ASIC/FPGA peeps, we are comparatively rare and it's nice to see that there are some of us here . Private message if you like