...good memory controller are VERY thin on the ground....
I don't doubt that producing a full up Apple like SoC is a huge task.
And why would a RISC-V, praised for its openness, want to have a proprietary memory controller?
Let's not confuse issues here James. There are standards and there are implementations.
The computing/software industry is rife with open standards, as is industry in general. Whether it be programming language standards, protocol standards, etc, etc. All the way down to the dimensions of metric nuts and bolts and the mass of a Kilogram.
These standards are beneficial to industry and trade, that is the way companies build stuff that inter-operates with the products of others, thus increasing the market for all.
These open standards don't generally dictate that the method of manufacture be open in turn. Quite often they are not.
So how does it come about that after all these decades the computing/software industry has not produced an open standard for one of the most important interfaces in the whole industry, that between the software and the hardware? It's shameful.
RISC V is a possible way to rectify that situation. Which is why so many around the world are cooperating on it.
It's going to be things like this that inhibit take up of new ISA's, because a good chip is not just an ISA.
As I say, I have no doubt that is true.
On the other hand I think it's a mistake to think the rest of the world cannot do it.
Now that ARM has sent a message to most ARM purchasers that they are not to be relied on as a supplier, there will be a lot of effort put in my many to get off that particular lock-in trap.
We are not talking about hobbyists tinkering at home with Verilog like me here. We are talking huge nation states and huge industries.
Memory in C++ is a leaky abstraction .