Heater
Posts: 14455
Joined: Tue Jul 17, 2012 3:02 pm

Re: RISC-V

Wed May 29, 2019 9:46 am

Gavinmc42,
RISC-V seem suitable for IoT/AIoT stuff but it is overkill and even dangerous to put Linux on these.
What on Earth is that supposed to mean?

One can build tiny RISC V chips that are suitable for the IoT requirements of small, low power, real-time, etc.

One can build RISC V chips loaded up with caches, virtual memory, memory protection etc, for full up operating systems like Linux.
Memory in C++ is a leaky abstraction .

Heater
Posts: 14455
Joined: Tue Jul 17, 2012 3:02 pm

Re: RISC-V

Wed May 29, 2019 9:52 am

lkcl,
Our team has received funding from the NLNet Foundation to develop a Libre RISCV SoC.
That sounds like an audacious project.

It would be nice if the page at https://libre-riscv.org/ actually said what it is about and who is doing it.
Memory in C++ is a leaky abstraction .

hippy
Posts: 6749
Joined: Fri Sep 09, 2011 10:34 pm
Location: UK

Re: RISC-V

Wed May 29, 2019 5:00 pm

Gavinmc42 wrote:
Wed May 29, 2019 2:30 am
RISC-V seem suitable for IoT/AIoT stuff but it is overkill and even dangerous to put Linux on these.
RISC-V is just an ISA specification. It can be turned into silicon which can fulfil the roles from simple microcontroller, through SoC's, to full blown PC CPU's, and probably super computers as well with appropriate instruction set extensions.

In fact one can design a minimal 8-leg microcontroller based on RISC-V and implement the bare minimum of instructions to get a specific job done if one wants. It's just that one can't actually sell it as "RISC-V" if doing that. There needs to be a certain level of instruction set supported to use the "RISC-V" name.

It wouldn't surprise me to see RISC-V based variants finding their way into Credit Card and other embedded places.

Linux would likely be overkill for a RISC-V product intended to compete against traditional 8-bit microcontrollers but, if it's a fast-track to getting the desired result, that's not really a problem.

It's like using a PI Zero to flash a LED. Total overkill for what needs to be done but a viable and cheap enough option in some cases.

And, with everything seemingly wanting to be IoT these days, needing some sort of Bluetooth, Wi-Fi or network capability, Linux is a sensible and fairly easy way to deliver that.

I'm not sure how you mean about "dangerous". It doesn't seem any more dangerous than putting Linux in any other product.

Heater
Posts: 14455
Joined: Tue Jul 17, 2012 3:02 pm

Re: RISC-V

Wed May 29, 2019 6:35 pm

hippy,
In fact one can design a minimal 8-leg microcontroller based on RISC-V and implement the bare minimum of instructions to get a specific job done if one wants. It's just that one can't actually sell it as "RISC-V" if doing that.
Sure you could. A square millimeter or two of silicon is enough to put a fully spec compliant RISC V processor on. It will fit in an 8 pin DIP package. All you nee to sell it as a RISC V is to join the RISC V Foundation and get it through whatever ISA test suite they have (Do they have yet?)

What a neat idea. A 8 pin DIP RISC V. A 555 timer on steroids!
Memory in C++ is a leaky abstraction .

hippy
Posts: 6749
Joined: Fri Sep 09, 2011 10:34 pm
Location: UK

Re: RISC-V

Fri May 31, 2019 1:35 am

jcyr wrote:
Thu May 30, 2019 6:49 pm
RISC-V is just an ISA specification. It can be turned into silicon which can fulfil the roles from simple microcontroller, through SoC's, to full blown PC CPU's, and probably super computers as well with appropriate instruction set extensions.
Not so sure about that later part! Is there a formal RISC-V extension supporting virtual addressing and privilege levels?
I don't know but there doesn't need to be. Manufacturers are free to invent whatever they want or need, and that doesn't have to be compliant with the RISC-V ISA per se. They could design their own ISA which just happens to include RISC-V as a subset of that.

Heater
Posts: 14455
Joined: Tue Jul 17, 2012 3:02 pm

Re: RISC-V

Fri May 31, 2019 3:00 am

jcyr,
Not so sure about that later part! Is there a formal RISC-V extension supporting virtual addressing and privilege levels?
There certainly is. See:

The RISC-V Instruction Set Manual
Volume I: Unprivileged ISA
Volume II: Privileged Architecture

Here:
https://github.com/riscv/riscv-isa-manual
https://github.com/riscv/riscv-isa-manu ... 21-21c6a14

There are already RISC V devices supporting the privileged architecture and running Linux and the like.

It world be crazy for a company to just create whatever they need here, it would be a huge effort and the result would not leverage all the existing (and future) RISC V tools and software. Basically it would defeat the point of them using the RISC V architecture standard in the first place.
Memory in C++ is a leaky abstraction .

User avatar
Gavinmc42
Posts: 4294
Joined: Wed Aug 28, 2013 3:31 am

Re: RISC-V

Fri May 31, 2019 3:50 am

What a neat idea. A 8 pin DIP RISC V. A 555 timer on steroids!
Smallest FPGA's are the Lattice 16pins? It's a bit small but it could be deadbugged.
Will RISC-V fit is those?
Any other potential chips?

One of the more useful Pi companions I use is the PSoC CY8C24123A, in 8 pin dip and SO8.
A modern version of that could be really useful.
I'm dancing on Rainbows.
Raspberries are not Apples or Oranges

mic_s
Posts: 92
Joined: Sun Oct 26, 2014 4:15 pm

Re: RISC-V

Fri May 31, 2019 8:32 am

Any other potential chips?
Low-end/lowcost RISC-V Microconroller from WinChip (WCH): CH572
(RISC-V, 60 Mhz, … , usb Host/Device, Bluethooth, 12bit AD, 3 Timers, 2 UARTs, SPI, WDOG ) Its not 8-pin, but QFN28
Smallest FPGA's are the Lattice 16pins?
Not at all. There are (not well known) 1.0*1.2 mm 8-pin FPGAs ( SLG46108 … ok .. thats only 4 LUTs, that woudn't give you the 32bit-RISC-V microcontroller you are asking for.

jamesh
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 24987
Joined: Sat Jul 30, 2011 7:41 pm

Re: RISC-V

Fri May 31, 2019 8:39 am

Do RISC-V specs also define a memory controller? Good ones are very difficult to design.
Principal Software Engineer at Raspberry Pi (Trading) Ltd.
Contrary to popular belief, humorous signatures are allowed. Here's an example...
“I own the world’s worst thesaurus. Not only is it awful, it’s awful."

mic_s
Posts: 92
Joined: Sun Oct 26, 2014 4:15 pm

Re: RISC-V

Fri May 31, 2019 9:33 am

JamesH wrote:Do RISC-V specs also define a memory controller? Good ones are very difficult to design.
Yes, difficult to design. A lot more than a simple state machine.

Currently there is only „The RISC-V Instruction Set Manual“
(Vol 1: Unprivileged ISA / Vol 2: Privileged Architecture )

That said, there are some remarks on memory related tasks in the specs:

Vol 1, chap 14, p81-87
„RISC-V Weak Memory Ordering“ (RVWMO)

Vol 1, chap 19, pxx
„Standard Extension for Transactional Memory“ is currently a stub

Vol 1, Appendix A, p161-189
Explanations for the mentioned RVWMO

Heater
Posts: 14455
Joined: Tue Jul 17, 2012 3:02 pm

Re: RISC-V

Fri May 31, 2019 9:34 am

RISC V is "only" an instruction set architecture (ISA) specification. The interface between software and hardware.

How one implements that ISA is entirely up to the implementer.

Funny you should mention memory controllers. Just now I'm trying to get my home brew RISC V to talk to a old fashioned 32MB SDRAM on an FPGA board. That simple thing is driving me nuts!

I'm pretty sure that a serious RISC V chip builder could find a good memory controller. Even if it is some proprietary IP block.
Memory in C++ is a leaky abstraction .

jamesh
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 24987
Joined: Sat Jul 30, 2011 7:41 pm

Re: RISC-V

Fri May 31, 2019 9:57 am

Heater wrote:
Fri May 31, 2019 9:34 am
I'm pretty sure that a serious RISC V chip builder could find a good memory controller. Even if it is some proprietary IP block.
You would be surprised.....good memory controller are VERY thin on the ground. Apple have their own custom one, it's very good, the Pi SoC's have custom ones IIRC.

And why would a RISC-V, praised for its openness, want to have a proprietary memory controller?

It's going to be things like this that inhibit take up of new ISA's, because a good chip is not just an ISA. There is a LOT of other stuff around them before you have a useful part. Especially something of the complexity of thre SoC's needed for a Pi like device.
Principal Software Engineer at Raspberry Pi (Trading) Ltd.
Contrary to popular belief, humorous signatures are allowed. Here's an example...
“I own the world’s worst thesaurus. Not only is it awful, it’s awful."

jdb
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 2215
Joined: Thu Jul 11, 2013 2:37 pm

Re: RISC-V

Fri May 31, 2019 10:17 am

Not just a memory controller - you need a SDRAM PHY of substantial complexity to talk to anything more complicated than PC133 SDRAM - DDR2 and onwards needs complicated lane deskew and impedance compensation. This part of the interface ends up being almost pure analogue logic and so far the "open source chip" designs haven't begun to offer alternatives there.
Rockets are loud.
https://astro-pi.org

hippy
Posts: 6749
Joined: Fri Sep 09, 2011 10:34 pm
Location: UK

Re: RISC-V

Fri May 31, 2019 10:50 am

jamesh wrote:
Fri May 31, 2019 9:57 am
And why would a RISC-V, praised for its openness, want to have a proprietary memory controller?
It's more that RISC-V don't care if a particular manufacturer chooses a proprietary controller for their chips.
jamesh wrote:
Fri May 31, 2019 9:57 am
It's going to be things like this that inhibit take up of new ISA's, because a good chip is not just an ISA. There is a LOT of other stuff around them before you have a useful part. Especially something of the complexity of thre SoC's needed for a Pi like device.
Broadcom, if they jumped aboard the RISC-V bandwagon, could simply rip out their ARM cores and replace them with RISC-V cores, still retain the proprietary VideoCore part and anything else proprietary which gives their chips an advantage.

Allwinner, MediaTek, Rockchip, Samsung and everyone else in that competing sector could do the same.

You are right, that for many SoC devices it's not the ISA which matters; in fact some would say that matters very little. So, looking from the other direction, there's no reason it has to be ARM and not something else.

Heater
Posts: 14455
Joined: Tue Jul 17, 2012 3:02 pm

Re: RISC-V

Fri May 31, 2019 11:06 am

jamesh,
...good memory controller are VERY thin on the ground....
I don't doubt that producing a full up Apple like SoC is a huge task.
And why would a RISC-V, praised for its openness, want to have a proprietary memory controller?
Let's not confuse issues here James. There are standards and there are implementations.

The computing/software industry is rife with open standards, as is industry in general. Whether it be programming language standards, protocol standards, etc, etc. All the way down to the dimensions of metric nuts and bolts and the mass of a Kilogram.

These standards are beneficial to industry and trade, that is the way companies build stuff that inter-operates with the products of others, thus increasing the market for all.

These open standards don't generally dictate that the method of manufacture be open in turn. Quite often they are not.

So how does it come about that after all these decades the computing/software industry has not produced an open standard for one of the most important interfaces in the whole industry, that between the software and the hardware? It's shameful.

RISC V is a possible way to rectify that situation. Which is why so many around the world are cooperating on it.
It's going to be things like this that inhibit take up of new ISA's, because a good chip is not just an ISA.
As I say, I have no doubt that is true.

On the other hand I think it's a mistake to think the rest of the world cannot do it.

Now that ARM has sent a message to most ARM purchasers that they are not to be relied on as a supplier, there will be a lot of effort put in my many to get off that particular lock-in trap.

We are not talking about hobbyists tinkering at home with Verilog like me here. We are talking huge nation states and huge industries.
Memory in C++ is a leaky abstraction .

Heater
Posts: 14455
Joined: Tue Jul 17, 2012 3:02 pm

Re: RISC-V

Fri May 31, 2019 11:25 am

hippy,
You are right, that for many SoC devices it's not the ISA which matters; in fact some would say that matters very little.
It seems paradoxical to me.

On the one hand who cares what the ISA is? That is why we have compilers, to abstract away the machine details and make code portable. That is why we have things like Java, compile once and run on whatever ISA by means of a VM. I'm used to being able to recompile projects and get them running on different architectures, all the way through Motorla 68000, to Power PC, to ARM, to Intel/AMD 32 and 64 bit and a few others along the way.

On the other hand, we clearly have a massive divide between the Intel PC software industry and the ARM mobile/embedded industry. Oddly enough it's the ISA very sharply delineates that divide. The ISA is critical.

Imagine a world where a common standard machine ISA was decided on by the industry decades ago. There would never have been any need for Java or .Net and so on. You have a binary, it runs.
Memory in C++ is a leaky abstraction .

jamesh
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 24987
Joined: Sat Jul 30, 2011 7:41 pm

Re: RISC-V

Fri May 31, 2019 11:54 am

Heater wrote:
Fri May 31, 2019 11:25 am
hippy,
You are right, that for many SoC devices it's not the ISA which matters; in fact some would say that matters very little.
It seems paradoxical to me.

On the one hand who cares what the ISA is? That is why we have compilers, to abstract away the machine details and make code portable. That is why we have things like Java, compile once and run on whatever ISA by means of a VM. I'm used to being able to recompile projects and get them running on different architectures, all the way through Motorla 68000, to Power PC, to ARM, to Intel/AMD 32 and 64 bit and a few others along the way.

On the other hand, we clearly have a massive divide between the Intel PC software industry and the ARM mobile/embedded industry. Oddly enough it's the ISA very sharply delineates that divide. The ISA is critical.

Imagine a world where a common standard machine ISA was decided on by the industry decades ago. There would never have been any need for Java or .Net and so on. You have a binary, it runs.
What really differentiates ARM from x86 is not the ISA, at least to average user. It's all the stuff around the ISA. As shown by Linux, which works fine on a number of different ISA's, but can be a right PITA because of the rest of the stuff in the chip (hence device tree) that needs to be supported. Not so bad on x86 desktop, but ARM devices are extremely fragmented. All sorts of stuff bolted on to the side of the ARMs.

You can simply recompile to get round ISA differences. You cannot do that for the other stuff (generally)
Principal Software Engineer at Raspberry Pi (Trading) Ltd.
Contrary to popular belief, humorous signatures are allowed. Here's an example...
“I own the world’s worst thesaurus. Not only is it awful, it’s awful."

Heater
Posts: 14455
Joined: Tue Jul 17, 2012 3:02 pm

Re: RISC-V

Fri May 31, 2019 5:58 pm

jamesh,
What really differentiates ARM from x86 is not the ISA... It's all the stuff around the ISA...You can simply recompile to get round ISA differences. You cannot do that for the other stuff (generally)
Yes indeed. Did I say it was paradoxical...

On the one hand...

a) The ISA is not the problem. We can recompile our code to run on pretty much anything useful now a days.

b) The ISA is not the problem. Being able to recompile code is only the beginning. It's all that other stuff ones OS and applications depend on that is the road block, peripherals, operating system etc.

On the other hand...

Riddle me this: Just now there is, to a first order approximation, a total dominance of the Intel/AMD ISA in the PC, server and super computer world. There is a total domination of the ARM ISA in the mobile/embedded world.

The ISA seems to be critical in this.

A paradox, the ISA is irrelevant, the ISA is central.

Anyway my observation is that it's absurd that all the worlds computing infrastructure is dependent on two companies. That is not a healthy or sustainable situation.
Last edited by Heater on Fri May 31, 2019 7:46 pm, edited 1 time in total.
Memory in C++ is a leaky abstraction .

hippy
Posts: 6749
Joined: Fri Sep 09, 2011 10:34 pm
Location: UK

Re: RISC-V

Fri May 31, 2019 7:16 pm

Heater wrote:
Fri May 31, 2019 11:25 am
On the other hand, we clearly have a massive divide between the Intel PC software industry and the ARM mobile/embedded industry. Oddly enough it's the ISA very sharply delineates that divide. The ISA is critical.
I disagree. It's that Intel chips are large, expensive, power vampires, and capable of melting most mobile phones if they used them. ARM chips aren't.

I don't believe that comes down to the ISA though how that ISA is implemented does have a bearing on things.

Intel will probably be the first to design RISC-V chips which can be used as toasters :lol:

User avatar
bensimmo
Posts: 4227
Joined: Sun Dec 28, 2014 3:02 pm
Location: East Yorkshire

Re: RISC-V

Fri May 31, 2019 7:39 pm

hippy wrote:
Fri May 31, 2019 7:16 pm
Heater wrote:
Fri May 31, 2019 11:25 am
On the other hand, we clearly have a massive divide between the Intel PC software industry and the ARM mobile/embedded industry. Oddly enough it's the ISA very sharply delineates that divide. The ISA is critical.
I disagree. It's that Intel chips are large, expensive, power vampires, and capable of melting most mobile phones if they used them. ARM chips aren't.

I don't believe that comes down to the ISA though how that ISA is implemented does have a bearing on things.

Intel will probably be the first to design RISC-V chips which can be used as toasters :lol:
The temperatures nothing compared to what the graphic processor people are vapourising.
I hear they've managed to make the humble hardrive in SSD format start to cook things too.

Saying that, my humble mobile phone chipset 'toaster' I.e. my phone if used hard, is uncomfortable.

Oddly of two similar age (old now) tablets, nvidia's tablet processor toasts and throttles almost instantly compared to Intels tablet processor. Their tablet processors where not to shabby. Guess it wasn't cost effective though, but they'll have had good research from it.

Just use what works in the design for the right price, its not as if you'd take a graphics chip and slap on a processor or four to it. That just seems a bit backwards...

Heater
Posts: 14455
Joined: Tue Jul 17, 2012 3:02 pm

Re: RISC-V

Fri May 31, 2019 8:13 pm

hippy,
I disagree. It's that Intel chips are large, expensive, power vampires, and capable of melting most mobile phones if they used them. ARM chips aren't.
That seems to be the case.
I don't believe that comes down to the ISA though how that ISA is implemented does have a bearing on things.
Ah, so you agree with me, the ISA is irrelevant.
Intel will probably be the first to design RISC-V chips which can be used as toasters
I would not have a problem with that.

As far as I can tell, high performance general purpose computing as we know it requires a lot of transistors and that they be switched really fast.

Power consumption increases with switching speed, and of course the number of transistors doing the switching.

In that respect, the ISA is again almost irrelevant, if you want the performance you will consume the power, no matter what ISA.
Memory in C++ is a leaky abstraction .

hippy
Posts: 6749
Joined: Fri Sep 09, 2011 10:34 pm
Location: UK

Re: RISC-V

Fri May 31, 2019 11:59 pm

jcyr wrote:
Fri May 31, 2019 9:13 pm
Where it does matter is as a widely adopted standard. Nobody's going to spend thousands of man hours creating an optimizing back end for GCC for some obscure ISA. The GNU tool chain has support for RISC-V which is a great start. Can't speak for the quality of the generated optimized code? Performance has as much to do with the compiler as it does with the silicon it runs on.
RISC-V has emerged from its chicken-egg situation in the same barren field all new arrivals find themselves in.

Interest is growing, tools are being developed and improved, cheap and reasonable silicon is arriving, and that in turn is drawing more into the fold. As interest grows, the interested numbers grow, that all feeds back into making things better and draws in even more.

A stunning back-end for GCC may not be there yet but, as time progresses, there's more likelihood it will bel. And that applies to its whole eco-system. And especially so given very large nation states really do seem committed to having it succeed.

So, unless something goes badly wrong, RISC-V looks set to be as much a self-fueling success as the Pi has been.

Heater
Posts: 14455
Joined: Tue Jul 17, 2012 3:02 pm

Re: RISC-V

Sat Jun 01, 2019 1:53 am

Like chickens and eggs I don't think RISC V arrived fully formed into a barren field. It evolved from the previous Berkeley RISC projects and others. It seems to have had a working GCC target since even before it had it's name and anyone outside knew it existed.

I agree compilers and other tools are critical to the adoption of any processor and the performance it can deliver.

In that respect RISC V has been doing very well for quite some time: "ISA Shootout – a Comparison of RISC V, ARM and x86:" https://www.youtube.com/watch?v=Ii_pEXKKYUg
Memory in C++ is a leaky abstraction .

lost
Posts: 28
Joined: Tue Dec 05, 2017 9:38 am

Re: RISC-V

Sat Jun 01, 2019 9:26 am

Heater wrote:
Sat Jun 01, 2019 1:53 am
In that respect RISC V has been doing very well for quite some time...
I think we must be careful. I was quite sure, by the end of the 1990's, PowerPC would be x86 killer. A newer&clean design, already thought to evolve nicely to 64bit (no need for another instruction set: Hello ARM!)...
But IBM opened the door for 2 years, Motorola semi-conductor at the time kicked in as they were moving ahead from 68k based chips, and big blue closed the door. They do not sell chips, but keep them for their own designs.

What may IMO help RISC V is x86 is now considered old&bulky, harmed by binary compatibility that is less useful in a world moving to open-source easily cross-compiled on whatever GCC supported target.

Then why not ARM? Maybe, but I think free software move will finally make it's way on hardware side & maybe Trump just helped a lot: At the moment, Huawei face it's dependency towards US&allies designs... But beside that, all the industry thinks "who's next?".

User avatar
bensimmo
Posts: 4227
Joined: Sun Dec 28, 2014 3:02 pm
Location: East Yorkshire

Re: RISC-V

Sat Jun 01, 2019 10:06 am

Lenovo, the hidden Chinese company.
It will need to give data just like HuaWei obviously, or is the name too western for Trump and he doesn't realise it's not IBM he's using with his Thinkpad.
Your TVs, Laptops, PCs, Servers, Phones, Moto, Medion (so anything electrical from Aldi)..

;-)
Last edited by bensimmo on Sat Jun 01, 2019 4:18 pm, edited 2 times in total.

Return to “General discussion”