Its always been available as __int128 in GCC.Heater wrote: ↑Mon Apr 23, 2018 11:21 amStrangely enough the RISC V specification includes a 128 bit version.
They were designing the ISA to be extensible in all kind of ways, including 32 bit and 64 bit operation, so they included the possibility of 128 bit, almost as a joke.
Turned out those guys building gigantic data warehouses are taking the idea seriously...
They already are. Because really, in any high level language, the number of bits on the underlying HW, for most people, is irrelevant. On the whole, the code I write is bit depth independent, unless using HW registers and even them, it's fairly irrelevant whether they are 8,16,32,64 or 128 bits in size.
If the idea of an open standard for the most important interface in computing, that between hardware and software, does not appeal to you than I don't think I can sell you on the idea.Apart from being open source, and hardware 128 bit integers, what does RISC-V offer that aarch64 on the Pi doesn't?
I'd be interested to hear the reasons for that preference.I took a quick look and preferred aarch64.
It does appeal, don't get me wrong. I was just wondering if there were any good technical reasons as well to get enthusiastic about.
It was some time ago, but one thing I do remember was the large number of "optional" features - which I really don't like (though I understand the reason why they are there). Unless the programmer/compiler just uses the guaranteed subset only, then its added complication.I'd be interested to hear the reasons for that preference.
I suspect that Intel chips are designed by guys out of Berkeley and such. They use optimizations invented in such places. I see no reason RISC V chips could not use the same....they can take on lessons learned from these other architectures,...
RISCV does not have an IPC. It's only an ISA spec. after all.Not sure of the instructions per clock to get with RISCV compared with x86 or ARMv8 but it's surely way behind at the moment.
Yes of course. I agree they are useful for just those reasons. x86 is just not in that market!Heater wrote: ↑Mon Apr 23, 2018 4:38 pmYes, all those RISC V options seem like a mess at first sight.
As you probably know having these standardized options is great. When I'm squeezing a RISC V into an FPGA I can make trade offs. Dump multiply and divide, use 16 or 32 registers etc, all the while knowing that my compiler, GCC or Clang, will support the thing.
Yes, ARM is a bit messy until aarch64 came along. But thats not true of x86 that I know of.I'd say the RISC V options are a lot less chaotic than the ever shifting instruction sets of x86 and ARM.
You certainly don't need it for twiddling an LED
Yes.Didn't the AAA instruction go away when AMD came up with the 64 bit version of x86?
Early days indeed. WhIch means the silicon implementations are not yet fast enough, and won't be until, probably, Pi6. And by that time, where will ARM be?Heater wrote: ↑Mon Apr 23, 2018 4:46 pmjamesh,
True enough, it's early days for RISC V.I suspect that Intel chips are designed by guys out of Berkeley and such. They use optimizations invented in such places. I see no reason RISC V chips could not use the same....they can take on lessons learned from these other architectures,...RISCV does not have an IPC. It's only an ISA spec. after all.Not sure of the instructions per clock to get with RISCV compared with x86 or ARMv8 but it's surely way behind at the moment.
Actual processors implementing that ISA may well have an IPC. The best of them, e.g. BOOM, are up there with ARM. Not bad going for the work of a bunch of grad students
That is a hint Pi4 will be ARM basedImagine, the Pi5 being slower than the Pi4. That'll sell. Not.
No Windows and no viruses is the biggest advantage.jamesh wrote: ↑Wed Sep 06, 2017 8:40 amOnly disadvantage, no Windows.feelslikeautumn wrote: ↑Wed Sep 06, 2017 6:40 amI don't think it necessarily works like that. From a ff bug report:
Of the 15m sold, a large number of raspberries will be sitting unused in drawer, a large number will be doing something embedded, a large number are too slow to do anything reasonable on a desktop. Pi usage will be a tiny percentage of the total number of Firefox users.
You may be interested to know that ARM originally meant Acorn RISC Machine. While complicated instructions have been added to recent models as well as Spectre-capable speculative execution (not the Pi), I think many still consider ARM in the tradition of a RISC design--at least it has a reasonably large set of registers.
This makes no sense in so many ways:Personally I couldn't care less for RISC until they have a usable processor competing in either the Intel/AMD Desktop market or the ARM based market.
For interest/amusement, Intel x86 Skylake has 180 physical integer registers and 168 vector registers.
My bad, I mean a RISC-V processor, not the architecture. I probably assumed, given the topic of talk (or a typo, it was a while ago now) the V would be there as I type.Heater wrote: ↑Thu May 10, 2018 5:29 pmbensimmo,This makes no sense in so many ways:Personally I couldn't care less for RISC until they have a usable processor competing in either the Intel/AMD Desktop market or the ARM based market.
The ARM is a RISC processor. In part and perhaps indirectly inspired by the work of Patterson and co. at UCB with their RISC architecture work back in the 1980's.
Intel and AMD essentially convert incoming instructions on the fly for their RISC engines to deal with efficiently.
If you mean the "RISC V" guys, well, they don't make a processor or any kind of chip. They just specify an instruction set that is open for anyone to use.
If you actually meant "RISC V", well yeah, I agree. Perhaps this whole idea takes off and we see people implementing RISC V machines with the performance you desire.
Or perhaps not...
In my dreams the Raspberry Pi Foundation is in just the right place to take on a RISC V design. For education's sake.
Either way, I'm having fun running a RISC V core on my FPGA boards, and now I'm trying to create my own RISC V core design.