Is Pi's flash memory memory mapped?

[lilzz]

Normally flash memory, rom memory can be memory mapped to DRAM main memory.

But since flash memory could be bigger than DRAM main memory, then how it could be mapped from something bigger to something smaller?

I read some where the main processor for Pi has internal sram, is that means the system doesn't DRAM main memory because sram can be used as main memory.

[fanoush]

As for memory mapping there are two levels -mapping to physical addresses and remapping physical addresses to virtual addresses which in Linux can be different for each running process.

Also please note that there in no flash memory directly in the Pi. Only the SD card which is separately managed by microcontroller inside the card and cannot be mapped to memory of the main CPU directly. Instead data from card is transferred via SD/MMC commands in blocks (of typically 512 bytes) to main SDRAM memory.

Then there is the virtual memory and how operating system manages it and as for Linux there is a mmap system call where you can map any linux file or device to the virtual memory so it appears like it is in memory while it is not. When your program tries to read/write the memory, the operating system will work behind scenes and communicate with the device so the correct part is read/written for you. Virtual memory is managed in pages (of 4KB typically).

mmap allows you to choose offset into file and size so if the file is larger than memory you can do it in parts

complicated? see e.g.
https://en.wikipedia.org/wiki/Virtual_memory
https://en.wikipedia.org/wiki/Memory-mapped_file

Normally flash memory, rom memory can be memory mapped to DRAM main memory.

well not exactly, memory (sdram,sram,rom,flash) can be mapped to memory space (i.e. some address range), you don't map one to another (rom to sdram).

But since flash memory could be bigger than DRAM main memory, then how it could be mapped from something bigger to something smaller?

on lowest physical level this is also done by paging, ie the CPU sees only part of the memory at one time.

I read some where the main processor for Pi has internal sram, is that means the system doesn't DRAM main memory because sram can be used as main memory.

SRAM is typicaly very small (like 256KB) so it is used only when main DRAM is not yet enabled (i.e. at boot time in bootloader before operating system is loaded), then it is also used as CPU cache (L1,L2) because it is fast, and sometimes as frame buffer for display (not in the Pi, it would not fit)

[W. H. Heydt]

I'm not 100% sure what you mean, but I'm going to take a shot at answering....

For this discussion, I'm going to ignore really specialized and extremely limited types of memory like registers.

The Pi SoC has a very small amount of Read Only Memory (ROM) that contains the first stage bootloader. It has (so far as I know) both level 1 cache memory (which would be Static Random Access Memory (SRAM) and level 2 cache SRAM. That memory is used to speed up memory access when working within a limited area. It has to be loaded from the "main" memory, which is a separate chip package of Dynamic Random Access Memory (DRAM). If the cache that contains data is altered, that has to be written back to main memory before that cache page can be reused (look up "dirty bit")

Any memory beyond that falls into the general category of "mass storage". Mass storage includes, flash--in all forms--HDDs, CDs, DVDs and so on.

In order to make it "look" to a program as if you have more main memory than is actually available, the OS "maps" pages onto mass storage. Other names for this is "virtual memory", "swap space" and "page table". By doing this, you can have multiple programs, each of which requires more memory than is really available, either for use, or absolutely. (That is, you could have a program that requires 2GB of memory running on a system with 1GB of main memory.) The BIG problem with doing this is that mass storage is much, much slower than main memory so the time it takes such a program to run will be far longer than you would otherwise expect.

The speed hierarchy is: L1 cache > L2 cache > L3 cache (if there is one) > main memory >> mass storage.