jamesh wrote:There are a number of options, all expensive (going to 28nm would be very very expensive). Adding gig ethernet, improving the memory controller, adding USB 3, adding quads (not necessarily an improvement interestingly) etc. All possible, al expensive.
I am curious though, how on earth did you guys manage to get the 2837 out so quickly? The initial cost of the 2836 was already incredible. If 3 million Pi 2s were sold, each unit would basically have to contribute around a dollar or so just to pay off the R&D on that chip. You guys seem to have bigger margins than I expected, or was Broadcom happy to help out?
I'm sure Eben is on the case!
Let me guess, the bcm2838 is currently being validated and soon to be shipped to TSMC
Let me first say a couple of things
1) I have no knowledge whatsoever about hardware design, rpi foundation plans, graphics gpus.
2) I think this thread should be locked or erased immediately!
Having said that my guesses are as follows:
I think vc4 has long been rather behind as from what I vaguely remember the data bus on vc4 is 128bit and I think mali is 256 and has been for some time, so bandwidth is going to be lacking for a lot of future stuff.
A new chip is unlikely, though people that I believe might know have said the vc5 gpu was complete before the project was dumped, but all the video codec stuff what stalled due to standards and licencing problems with h265.
I have no idea what that means.
I think adding new ARM cores onto the vc4 die is relatively easy thats why broadcom churns them out so quick.
Things that take time would be scaling to a smaller silicone die feature size, redesigning the data bus, adding pipelines for more qpu gpu processors, redsigning the dma system which is very important part of moving large amounts of data around, etc etc etc...
I have no idea about all that, it is way too complex for anyone on this forum and thinking about it will change nothing.
So what I hope is, Broadcom invests in some amazing flexible I/O hardware dma gpio system that can handle shifting out extreamly high speed 10GHz serial data on any and all gpio pins allowing usb 3.1/SDXC UHS2/SDIO on any and every external connection with loads of clock options etc.
Then they need to bump the data bus to 512bits wide stack on 16x more qpu that in the VC4, reduce the die feature size to 14nm and multiply the clock speed by 4, then implement Vulkan and h266 drivers.
Finally when the rpi foundation design the board they need to add a multiprocessing cluster chip stacking interconnect, SD card raid bus for 8 ultra uSD cards, mcu IO coprocessor with multi channel ADC and DAC and shared memory, 32Gb pop memory, and liquid cooling quick connectors.
Now please lock the thread!