W. H. Heydt wrote:
I do agree that having an independent bus for Ethernet would be a Good Thing. It's number two on the list of things I'd like to see in some future Pi. For what it's worth, my number one "like to have" feature would be a SATA port, but that is probably a pretty small minority view.
I'd put those things pretty high on my list as well (along with the usual better processor cores, more ram, better bus connecting them)
Thanks for the vote of confidence in my wish list. Of course--as my father used to say (a *long* time ago!)--that and a dime will get you a cup of coffee.
I really can't see more cores being useful unless there is a radical change somewhere. I know there are 8-core SBCs around now, but they all seem to be using the ARM LITTLE-big architecture, and that mostly amounts to 4 usable cores most of the time.
It will be interesting to see what they come up with for the next generation of pi (and no I don't have any inside information on it at this time). It seems pretty clear to me that it would be pointless to just bolt better processor cores onto the current SoC design, they got away with doing that once but not a second time. So the question then becomes whether they will be able to persuade broadcom to design a chip primerally for them that upgrades the GPU, busses etc while keeping the GPIO perhiperals as similar as possible or whether they will have to go with something off the shelf that is totally incompatible with their current design.
Hard to say. I have my suspicions that the RPF *might* be able to go to Broadcom with enough money to have a chip designed to their own spec...but that suspicion depends on numbers I haven't seen, so it's really pure guesswork.
For the next iteration, I think the VC4 is going to be the bottleneck. Either there is going to have to be some way to drastically (like 2x to 4x) to speed it up, or it's going to be necessary to pick a chip with a different--and significantly more capable GPU. That is going to have some major consequences for Pi software, though.
Now *if* I had the money to do a custom design, I can think of some things I'd be after. Besides my actual wish list (SATA, Ethernet bus, RTC), I'd want at least 2 more address lines as 1GB is a little tight on RAM for 4 cores, especially at a higher clock speed. next I'd be looking at a significantly fast clock, say in the 1.5GHz range. Given that the quad-A5 Odroid-C1 running at 1.5GHz only benchmarks around 10% to 20% faster than the quad-A7 Pi2B at 900MHz, going for quad-A7 (or better) at 1.5GHz would be a really fast system for an SBC.
Note that being able to address 4GB doesn't mean that boards would have to be built with that much RAM, but it would permit boards with more memory to follow as price points permitted. This is similar to the situation where the current full boards have one camera connector, but the SoCs can have two...and the CM makes both interfaces available.
In the very long run, say 10-plus years out, one has to consider the possibility of moving to 64-bit cores. At that point, a larger memory model is probably going to become a "must have".