People who complain about current software tools should write something better or be quiet.
I can appreciate that. As such can I downgrade what I said from "complaint" to "observation"?
My observation is that many of today's development tools are obscenely huge, complex and slow. Demanding a lot of effort to find your way around them. In short, time wasting and tedious. It's not entirely clear to me that all of that is necessary.
Further, it's not just the editors and IDEs. This issue stems from the very languages, compilers, run times and build systems. It's systemic. It's not something I or any regular developer can fix to satisfy himself, far too big a task.
For the sake of brevity I'll restrict my complaint, err observation, to two cases that have been bothering me this weekend and wasted many hours of my life:
1) Altera's, now Intel's Quartus dev tools for FPGA:
If you want to toy with FPGA you need Quartus or similar HDL dev tools from the FPGA vendor. Oh my God, they are gigabytes of download and install, they take forever to become familiar with, the actual editors are terrible and the edit, build test cycle is mind bendingly slow. Sure they are very feature packed. But really.
As it happens we now know this need not be the case as Clifford Wolf and friends have produced FPGA tool chains for Lattice FPGA's that are orders of magnitude smaller and faster whilst also being very simple to use.
2) Scala, Java, IntelliJ, SBT...
If you have toyed with FPGA a bit you soon find that the hardware description languages, Verilog and VHDL, are a pain. So I thought I try something a bit more high level, SpinalHDL. Now Spinal is a Scala library. That means getting familiar with Scala. But Scala is not a real language, it compiles to Java bytecode and depends on the Java libraries. That means needing all that stuff. The whole concoction is so complex that it's almost impossible to write code without an IDE to guide you, that pulls in InteliJ and SBT as the build system.
Before you know it you are up to your eyeballs in complexity and having a hard time making the pieces work together. And of course compilation is tediously slow (That is not actually compilation, just generating Verilog from VHDL from Spinal/Scala). And noticing that a simple job requires 3GB of RAM!
Luckily again we now know this need not be so. Someone has a plan to fix this. Per Vognsen has made great progress in creating a high level HDL in Python. Not done yet.
Oops, sorry, said I stick to two complaints/observations.