Correct me if i`m wrong but the Ethernet on the board is driven by a seperate chip
An ethernet controller is logically seperated into two parts. The MAC (medium access controller) and the PHY (physical layer). It is almost unheard of to see a PHY on a "SoC" as they require different semiconductor processes to implement well. So there are two common patterns for Ethernet support. One pattern is to have the MAC on the SoC and then have a seperate PHY chip. The other pattern is to integrate the MAC with the PHY.
If the MAC is part of the SoC then clearly you are limited to the choices the SoC designer made. If the MAC is seperate from the SoC then you have to connect it to the SoC somehow. You could connect a gigabit controller over USB2 but you won't come anywhere near to maxing it out if you do.
So if you actually want gigabit speeds then you need a SoC which either has gigabit ethernet built in or has a fast interface to which you can connect a gigabit ethernet MAC without creating a bottleneck. Such SoCs do exist but they tend to be either expensive or have weak processor cores that make them unsuitable for much more than dumb NAS work.
A further big problem is that doing stuff in small volumes significantly increases the cost per unit both because any of your own fixed costs need to be spread among fewer units and because the people who actually build it for you charge a lot more per unit for small runs (to recoup THEIR fixed costs). The reason the raspberry Pi is so cheap is because of a combination of the engineers donating their time for free and the foundations backers sticking their necks out and funding an initial production run of TEN THOUSAND units out of essentially their own pockets.