[moderator] Its now 2019, and the contest is over.
I don't see how anyone could create an entry to this competition in the time available, surely the winner will be an existing design adapted to the competition rules.
Google for DarkRisc-V, the author claims to do it from scratch over one night.
I have always wanted to get into FPGA's but boards have historically been quite expensive, even prohibitively expensive, for someone who just wants to earn the 'done that' T-shirt.
Yes, also the 1.0 version is missing few capacitors for stability and GND line is very thin, some people call the design horrible. The 2.0 version is improved after some feedback. And ftdi chip makes it easier. Definitely go for 2.0 unless you want cheapest and smallest and are prepared to flash it over SPI and possibly also add 1, 2 or 3 smd capacitors yourself.
Yes.I'm guessing the $13.99 version 2.0 board with a USB programming connector would be the best choice if also looking at developing on a PC ?
You are right. But a low number of the required LOC (Verilog or SpinalHDL or ...) for your rv32i-core is a measure for „doable“ in a short time frame.I'm not sure we should worry about LOC so much. It's FPGA usage that matters at the end of the day.
YES … and no. (note the upper and lower case)it all boils down to nothing when synthesized. I'm very sure these compilers do a better job of minimizing logic than I can.
Take it as an additional chance to learn new things. BTW: Zyphyr isn't rocket science, If your core pass the RISC-V RV32I compliance tests, there will be no problem at all: It will do zyphyr by design. The two examples („Philosophers“, „Synchronization“) mentioned in the description are real small examples (think of it as „Hello World“ examples). They are chosen, so the intern mem of small FPGAs will hold the code.I don't have time to mess with some OS I have never heard of. I don't even want an OS in my creations.
When I got upduino 1.0 I have rebuilt IceStorm toolchain with yosys, arachne-pnr directly on the Pi3. It run over night but finished successfully after many hours (with rootfs on ssd over USB). Later I also manged to rebuild riscv gcc toolchain and micropython https://github.com/mmicko/micropython/t ... s/picorv32 on the Pi3. I did it on the pi primarily because of easier SPI flashing. With 2.0 upduino version I'd probably go with linux PC as building geverything on pi is a bit slow and also the synthesis is cpu intensive. However it is definitely doable just with the Pi.
Quite so. I'm really liking SpinalHDL as it is so much nicer to be able to design logic in a nice readable, expressive, high level language than Verilog or VHDL. One neat thing is that Spinal compiles down to Verilog and one can easily see how much code one is generating.a low number of the required LOC (Verilog or SpinalHDL or ...) for your rv32i-core is a measure for „doable“ in a short time frame.
Multiple clock domains and PLL's are problems I have yet to tackle. Thanks I'll keep an eye out for that if/when I get there....current tools have a lot of problems with border-crossing (e.g. two or more clock-domains) or with PLLs o
Ah yes. I'm up for that.Take it as an additional chance to learn new things.
fanoush wrote: When I got upduino 1.0 I have rebuilt IceStorm toolchain with yosys, arachne-pnr directly on the Pi3. It run over night but finished successfully after many hours (with rootfs on ssd over USB)
If anyone is interested in FPGA and want to test a real low-cost one, upduino 1 or 2 is an option. Concerning development tools the mentioned Open Source is another option. BTW. : Lattice as released a new ide, called Radon : Verilog/VHDL with Synplify Pro or LSE, Reveal, Aldec Active-HDL etc. … - its Diamond like. It works with Upduino. One-year-license is free.heater wrote: But then I got curious about FPGA, logic design, CPU design...Especially as they are now readily available and so cheap and especially now that we have Open Source tools. Discovering that we don't need to fight with those huge, bloated, complex, slow, development tools from the FPGA vendors to get started was an eye opener. So much easier to kick around with Icarus and the Verilator.
Wow 13+ hour build, 2.6GB left of 32Gb - Gentoo64 OS.
"Nothing to be done..." Can I assume it's is all done?
Gee what if I missed something and have to rebuild?
riscv-gnu-toolchain folder is 279645 files totally 12GB
Having just got back to looking at RISC-V / FPGA I decided to install the same toolchain and that was pretty easy with Pi packages available, mere seconds to get a simple example done -
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sudo apt-get install yosys sudo apt-get install arachne-pnr
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module top(input A, input B, output X); assign X = A & B; endmodule
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set_io A 1 set_io B 2 set_io X 3
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yosys -q -p "synth_ice40 -blif example.blif" example.v arachne-pnr -p example.pcf example.blif -o example.asc icepack example.asc example.bin icetime -tmd hx1k example.asc iceprog example.bin
That's my goal, and I can't see why not.
Sure there are, though not necessarily useful or sensible. I should know; I've designed plenty