mic_s
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Design your own 8$-RISC-V (may work with your pi)

Sat Oct 13, 2018 7:04 pm

If you are interrested to design your own RISC-V-Microprocessor / program in verilog, VHDL / this may be for you (the smallest FPGA-Harrdware-development system is available for 8$)

details:
https://riscv.org/2018contest/
( win up to USD $6,000, hurry up )

[moderator] Its now 2019, and the contest is over.
.

Heater
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Re: Design your own 8$-RISC-V (may work with your pi)

Sat Oct 13, 2018 8:11 pm

I started my own RISC-V implementation back in April. There is no way that it's going to be completed by the closing date of this competition.

https://github.com/ZiCog/sodor-spinal

Not that my humble effort would compete on speed, it has no pipelinning or caches etc. I'm sure someone could find a way to make a smaller design as well.

My humble effort is only intended as a way to get familiar with the RISC V ISA and learn how to design logic using the SpinalHDL hardware description language. http://spinalhdl.github.io/SpinalDoc/ To that end I'm keeping everything as simple as possible.

I don't see how anyone could create an entry to this competition in the time available, surely the winner will be an existing design adapted to the competition rules.

mic_s
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Re: Design your own 8$-RISC-V (may work with your pi)

Sat Oct 13, 2018 9:13 pm

You are right. This is not for the beginner. It is meant for the skilled Verilog/VHDL/FPGA-Programmer.
I don't see how anyone could create an entry to this competition in the time available, surely the winner will be an existing design adapted to the competition rules.

May be. … But there are also low hanging fruits: you can do your own RISC-V (Note: only Integer-Variant is required) in a few hundred Verilog LOC for a very, very small FPGA ( e.g. iCE40UP5K-SG48I )
Clifford and others demonstrated that:

http://www.clifford.at/
https://github.com/cliffordwolf/picorv32

Nice idee:
Design something like the mentioned minimal Integer-Risc-Vs as an add on for a Pi-Zero and do communication between Pi and your RISC-V via SMI or SPI. Your total Investment (beside your time) is 8 USD (UPDuinoBoard V1). Thats realy low cost.

mic

Heater
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Re: Design your own 8$-RISC-V (may work with your pi)

Sat Oct 13, 2018 10:46 pm

I think the idea has lots of possibilities.

I got a picorv32 core running on DE-0 Nano board a year ago. https://github.com/ZiCog/xoro As I was new to Verilog I just cut out the picorv32 core and started surrounding it with my own memory and peripheral interfaces. Didn't take much time at all to get it running at 100MHz and communication via my home made UART module.

I was thinking to get it running on a cheap Lattice board as a peripheral chip. But then I got diverted by the idea of creating my very own RISC V core from scratch in SpinalHDL. Creating ones own processor is something every self respecting nerd should do, right? See sodor-spinal link above.

The thing about the competition is that even if you are skilled at Verilog I get the feeling that creating a new processor core from scratch is going to take more time than is available.

My completed sodor core runs to 870 lines of Spinal source code. Could have been about 600 had I been less verbose but I wanted it to be very clear to read. It would generate the same amount of logic in the end. Anyway, judging by the commit log in my github repository that core took me about 13 days.

The picorv32 core runs to 2000 lines of Verilog.

The idea of connecting an FPGA to the SMI is interesting...

fanoush
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Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 6:13 am

Heater wrote:
Sat Oct 13, 2018 10:46 pm
The thing about the competition is that even if you are skilled at Verilog I get the feeling that creating a new processor core from scratch is going to take more time than is available.
Google for DarkRisc-V, the author claims to do it from scratch over one night.

Heater
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Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 6:52 am

fanoush,

Thanks for the heads up on darkriscv.

Wait a minute, a bit of exaggeration going on there, darklife does go on to say

"after weeks of exciting sleepless nights of work...the darkriscv reached a very good quality result, in a way that the "hello world" compiled by the standard riscv-elf-gcc is working fine! :)"

and

"The general concept is based in my other early RISC processors..."

The github commit history shows a lot more than a nights work.

Having said that, darkriscv sounds cool and pretty impressive. I might borrow some of his ideas for my effort :)

The more the merrier I say. It will be an interesting competition.

mic_s
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Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 1:11 pm

Number of Verilog-LOC for a rv32I-core ?

Interesting question. The mentioned darkriscV-core is 360 LOC ( Note: darkrisc dos't implement all Integer-Instructions yet … there are errors ... work in progress … i'm not envolved but it looks like darkrisc is a moving target … so final there will be a little bit more LOC )
Anyway, it is possible to implement a basic Risk-V rv32I-core (must pass the RISC-V RV32I compliance tests) with a few hundreds LOC.

If anyone is interested in the contest … read the instructions (https://riscv.org/2018contest/) carefully - Especially the paragraph „Minimum Requirements“ … Think about it ... Read it a second time … depending on your knowlage ... may be some Zeyphr-RTOS-learning is required.

I'm not allowed to participate but here are my hints:

(1) Try to design your very basic risc-V for the “smallest implementation” category. Do this for the Lattice 5K 4-input LUT „iCE40 Ultra Plus“ AND for the Microsemi IGLOO2 M2GL025 or SmartFusion2 M2S025. This way you double your points.

(2) In a second step, you may design an optional "Extra" (SMI-slave-interface, Low-Pin-Count-controller for external memory, ... ). May be this will bring you extra points.

Good luck.

and ... have fun with Verilog, FPGA and risc-V

.

Heater
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Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 4:21 pm

I'm not sure we should worry about LOC so much. It's FPGA usage that matters at the end of the day. My RISC V core source code is kind of verbose, in order to make it clear to the human reader, but it all boils down to nothing when synthesized. I'm very sure these compilers do a better job of minimizing logic than I can. Unless I'm ordering up a ton of pipeline registers and such.

Especially if one is using a higher level language like Chisel or Spinal. That is like comparing lines of code between assembler language and C++.

I'm curious, why are you not allowed to participate? Are you connected to the competition organizers or restricted by your employers NDA's or what?

You are right, the competition instructions are tough. I don't have time to mess with some OS I have never heard of. I don't even want an OS in my creations.

hippy
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Location: UK

Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 5:06 pm

mic_s wrote:
Sat Oct 13, 2018 9:13 pm
Your total Investment (beside your time) is 8 USD (UPDuinoBoard V1). Thats realy low cost.
I have always wanted to get into FPGA's but boards have historically been quite expensive, even prohibitively expensive, for someone who just wants to earn the 'done that' T-shirt.

I have crafted quite a few designs for very simply microcontroller cores over the years and have always wanted to turn at least one into actual silicon. I think I know what I'd like my next adventure to be. Time to see what tools are available for development on a Pi.

I'm guessing the $13.99 version 2.0 board with a USB programming connector would be the best choice if also looking at developing on a PC ?

fanoush
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Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 6:56 pm

hippy wrote:
Sun Oct 14, 2018 5:06 pm
I'm guessing the $13.99 version 2.0 board with a USB programming connector would be the best choice if also looking at developing on a PC ?
Yes, also the 1.0 version is missing few capacitors for stability and GND line is very thin, some people call the design horrible. The 2.0 version is improved after some feedback. And ftdi chip makes it easier. Definitely go for 2.0 unless you want cheapest and smallest and are prepared to flash it over SPI and possibly also add 1, 2 or 3 smd capacitors yourself.

BTW, This was first time I soldered SMD parts. I was very happy it worked but I prefer to avoid such adventure next time. Here is my result
upduino1caps.jpg
upduino1caps.jpg (45.95 KiB) Viewed 4334 times
the third one is on second voltage regulator on the other side of the board.
Last edited by fanoush on Sun Oct 14, 2018 7:33 pm, edited 1 time in total.

mic_s
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Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 7:23 pm

I'm guessing the $13.99 version 2.0 board with a USB programming connector would be the best choice if also looking at developing on a PC ?
Yes.
I'm not sure we should worry about LOC so much. It's FPGA usage that matters at the end of the day.
You are right. But a low number of the required LOC (Verilog or SpinalHDL or ...) for your rv32i-core is a measure for „doable“ in a short time frame.
it all boils down to nothing when synthesized. I'm very sure these compilers do a better job of minimizing logic than I can.
YES … and no. (note the upper and lower case)
YES, generally it will do a fine job.
No, when it comes to the details: e.g. current tools have a lot of problems with border-crossing (e.g. two or more clock-domains) or with PLLs or …
I don't have time to mess with some OS I have never heard of. I don't even want an OS in my creations.
Take it as an additional chance to learn new things. BTW: Zyphyr isn't rocket science, If your core pass the RISC-V RV32I compliance tests, there will be no problem at all: It will do zyphyr by design. The two examples („Philosophers“, „Synchronization“) mentioned in the description are real small examples (think of it as „Hello World“ examples). They are chosen, so the intern mem of small FPGAs will hold the code.

.

fanoush
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Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 8:44 pm

hippy wrote:
Sun Oct 14, 2018 5:06 pm
Time to see what tools are available for development on a Pi.
When I got upduino 1.0 I have rebuilt IceStorm toolchain with yosys, arachne-pnr directly on the Pi3. It run over night but finished successfully after many hours (with rootfs on ssd over USB). Later I also manged to rebuild riscv gcc toolchain and micropython https://github.com/mmicko/micropython/t ... s/picorv32 on the Pi3. I did it on the pi primarily because of easier SPI flashing. With 2.0 upduino version I'd probably go with linux PC as building geverything on pi is a bit slow and also the synthesis is cpu intensive. However it is definitely doable just with the Pi.

I did not try newer yosys/nextpnr/trellis tool set yet. It supports also much faster ECP5 lattice FPGA family. The Ultraplus family is low power, low price, low performance - good enough, but nontrivial designs top at 24-30Mhz max (which is still plenty for learning and lot of real stuff).

Heater
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Re: Design your own 8$-RISC-V (may work with your pi)

Mon Oct 15, 2018 2:39 am

mic_s,
a low number of the required LOC (Verilog or SpinalHDL or ...) for your rv32i-core is a measure for „doable“ in a short time frame.
Quite so. I'm really liking SpinalHDL as it is so much nicer to be able to design logic in a nice readable, expressive, high level language than Verilog or VHDL. One neat thing is that Spinal compiles down to Verilog and one can easily see how much code one is generating.
...current tools have a lot of problems with border-crossing (e.g. two or more clock-domains) or with PLLs o
Multiple clock domains and PLL's are problems I have yet to tackle. Thanks I'll keep an eye out for that if/when I get there.
Take it as an additional chance to learn new things.
Ah yes. I'm up for that.

Thing is, having had to learn and use a new programming language and/or operating system every two years for forty years I got a bit jaded about it all. That might be a bit of an exaggeration, I'm not about to count them all. The prospect of having to become familiar with yet another f..ing language/OS to get something done starts to seem like a chore. A change without a difference. So much so that I kind of promised myself I'd never consider learning a new language again for what remains of my life.

But then I got curious about FPGA, logic design, CPU design...Especially as they are now readily available and so cheap and especially now that we have Open Source tools. Discovering that we don't need to fight with those huge, bloated, complex, slow, development tools from the FPGA vendors to get started was an eye opener. So much easier to kick around with Icarus and the Verilator. And of course the arrival of the RISC V is a great incentive to delve into this world.

So this last year has called for learning yet another f..ing language. In fact two of them, Verilog and Scala (SpinalHDL). Which has actually been quite a blast as what one is doing there when putting logic together is rather different to typical sequential programming. One has to think a bit differently.

So, things like Zyphyr are not off my table exactly, it's just that I'm not seeing the "shiny" in there to attract my attention yet.

mic_s
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Re: Design your own 8$-RISC-V (may work with your pi)

Mon Oct 29, 2018 9:10 am

fanoush wrote: When I got upduino 1.0 I have rebuilt IceStorm toolchain with yosys, arachne-pnr directly on the Pi3. It run over night but finished successfully after many hours (with rootfs on ssd over USB)
heater wrote: But then I got curious about FPGA, logic design, CPU design...Especially as they are now readily available and so cheap and especially now that we have Open Source tools. Discovering that we don't need to fight with those huge, bloated, complex, slow, development tools from the FPGA vendors to get started was an eye opener. So much easier to kick around with Icarus and the Verilator.
If anyone is interested in FPGA and want to test a real low-cost one, upduino 1 or 2 is an option. Concerning development tools the mentioned Open Source is another option. BTW. : Lattice as released a new ide, called Radon : Verilog/VHDL with Synplify Pro or LSE, Reveal, Aldec Active-HDL etc. … - its Diamond like. It works with Upduino. One-year-license is free.
.

mic_s
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Re: Design your own 8$-RISC-V (may work with your pi)

Tue Dec 18, 2018 8:02 pm

… and the winners are :

1. Place: Charls Papon with VexRiscv-Variants (SpinalHDL-based).
GitHub: https://github.com/SpinalHDL/VexRiscvSo ... ontest2018
$6,000 USD

2. Place: Antti Lukats with „Engine-V“.
GitHub: https://github.com/micro-FPGA/engine-V
$3,000 USD

3. Place: Changyi Gu with „PulseRain Reindeer“,
GitHub: https://github.com/PulseRain/Reindeer
$1,000 USD

and „free style“ :

Creative Prize: Olof Kindgren with SERV (Bit-Serial-RiscV),
GitHub: https://github.com/olofk/serv
$3,000 USD

Congretulations.

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Gavinmc42
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Re: Design your own 8$-RISC-V (may work with your pi)

Fri Jan 04, 2019 1:03 am

Even found an Editor with built in github stuff. (stuff is my catch word for things on my list still to be mastered)
https://tinyfpga.com/bx/guide.html

Yep looks like it is time to learn FPGA's :(
Even learn how jpeg works?
https://github.com/develone/JPEG_Encoder
https://ultibo.org/forum/viewtopic.php? ... a&start=30

When I start seeing the same message from various places it is a sign I have missed a change in technology.
Open source FPGA :D
I'm dancing on Rainbows.
Raspberries are not Apples or Oranges

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Paul Webster
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Re: Design your own 8$-RISC-V (may work with your pi)

Fri Jan 04, 2019 6:06 pm

Interesting that RPF has joined RISC-V group.

fruitoftheloom
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Re: Design your own 8$-RISC-V (may work with your pi)

Fri Jan 04, 2019 6:21 pm

Paul Webster wrote:
Fri Jan 04, 2019 6:06 pm
Interesting that RPF has joined RISC-V group.


viewtopic.php?f=63&t=230462
adieu

My other Computer is an Asus CS10 ChromeBit
https://www.asus.com/uk/Mini-PCs/Chromebit-CS10

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Gavinmc42
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Re: Design your own 8$-RISC-V (may work with your pi)

Sun Jan 06, 2019 6:14 am

I made a comment the other day about something Pete Warden said a while back.
Low cost low power vision etc.
You guys got me curious about these FPGAs and look what I found
http://www.latticesemi.com/en/Products/ ... imaxHM01B0

Really tiny smart cameras?
Optical flow drone collision avoidance....

Installing RISC-V tools on a Gentoo64 Pi :D
Quoting myself from another post ;)
Wow 13+ hour build, 2.6GB left of 32Gb - Gentoo64 OS.
"Nothing to be done..." Can I assume it's is all done?
Gee what if I missed something and have to rebuild?
riscv-gnu-toolchain folder is 279645 files totally 12GB :D
I'm dancing on Rainbows.
Raspberries are not Apples or Oranges

hippy
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Location: UK

Re: Design your own 8$-RISC-V (may work with your pi)

Tue Feb 19, 2019 12:05 am

fanoush wrote:
Sun Oct 14, 2018 8:44 pm
When I got upduino 1.0 I have rebuilt IceStorm toolchain with yosys, arachne-pnr directly on the Pi3. It run over night but finished successfully after many hours (with rootfs on ssd over USB).
Having just got back to looking at RISC-V / FPGA I decided to install the same toolchain and that was pretty easy with Pi packages available, mere seconds to get a simple example done -

Code: Select all

sudo apt-get install yosys
sudo apt-get install arachne-pnr
nano example.v

Code: Select all

module top(input A, input B, output X);
  assign X = A & B;
endmodule 

nano example.pcf

Code: Select all

set_io A 1
set_io B 2
set_io X 3
Then

Code: Select all

yosys -q -p "synth_ice40 -blif example.blif" example.v
arachne-pnr -p example.pcf example.blif -o example.asc
icepack example.asc example.bin
icetime -tmd hx1k example.asc
iceprog example.bin

Heater
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Re: Design your own 8$-RISC-V (may work with your pi)

Tue Feb 19, 2019 12:34 am

That's great.

Now that you have proved the tool chain with a "hello world", what about trying to build a RISC V? I wounder if it can be done within the confines of the Pi.

I managed to get Clifford Wolf's picorv32 working easily enough using the Altera tools , which surprised me as I knew nothing of Verilog before I started: https://github.com/cliffordwolf/picorv32

hippy
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Re: Design your own 8$-RISC-V (may work with your pi)

Tue Feb 19, 2019 11:55 am

Heater wrote:
Tue Feb 19, 2019 12:34 am
what about trying to build a RISC V? I wounder if it can be done within the confines of the Pi.
That's my goal, and I can't see why not.

The UPDuino brings FPGA development within the price range of most people, and thanks again to mic_s for bringing that to our attention.

But I had somehow got the impression that yosys and the toolchain weren't necessarily going to be easy to get to grips with. Turns out otherwise and the toy example above is mainly to provide others with a fast-track to giving it a whirl if they were also procrastinating or, like me, were thinking it could all be too hard to ever consider. I find there's nothing like 'wow; that was easy!" to motivate people and get them hooked :D

I have never used an FPGA before so it's going to be a learning curve but the toolchain being so easy has encouraged me; there's nothing stopping me getting started, even without FPGA hardware.

Before my own RISC-V FPGA venture it's going to be 'flash a LED', 'detect a button', 'beep a piezo' and getting the usual things under my belt, learning as I go. I will likely implement a simpler CPU before something more complicated. I'll document my adventures as I go.

Heater
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Re: Design your own 8$-RISC-V (may work with your pi)

Tue Feb 19, 2019 2:08 pm

hippy,

For sure the yosys tool chain is a lot simpler and quicker to use than struggling with the huge and complex tools the FPGA vendors supply.

My "wow, this can be simple" moment came when I discovered the Icarus Verilog simulator: http://iverilog.icarus.com/ With Icarus one can start with some simple Verilog module, intended for FPGA, create a little test "bench" top level module for it and then simulate it very quickly from the command line. It's such a quick edit/run cycle it's like hacking on Python code. It also produces wave form files that can be viewed in gtkwave so that one can see exactly how your timing is going. http://gtkwave.sourceforge.net/

I think you have a great plan there to start simple and write up you progress. If you can get gates, counters, memory blocks, multiplexers, decoders, working you suddenly find you have all the means to make all the blocks required to construct a CPU.

I'm not sure there is a CPU much simpler than a basic RISC V. I started on my own CPU effort following the simple Sodor single stage RISC V design. See the block diagram here: https://github.com/ucb-bar/riscv-sodor/ ... 1stage.pdf The advantage of going straight to RISC V is that you have assemblers and compilers available to get some code running on it.

I do worry that the Pi will run out of memory when building something that big...we shall see.

hippy
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Re: Design your own 8$-RISC-V (may work with your pi)

Tue Feb 19, 2019 3:29 pm

Heater wrote:
Tue Feb 19, 2019 2:08 pm
I'm not sure there is a CPU much simpler than a basic RISC V.
Sure there are, though not necessarily useful or sensible. I should know; I've designed plenty :lol:

A 'one instruction computer' appeals to me, especially as some have compilers, but I prefer stack-based architectures with more traditional operators.

https://en.wikipedia.org/wiki/One_instr ... t_computer

RISC-V takes the sensible approach of aiming to be useful and providing for all which needs to be done with a lot of work put into figuring out how that should optimally be done. For most hobbyists who aren't looking for world domination it's more a case of finding a balance between being easy to implement and usable enough, having fun along the way.

Heater
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Re: Design your own 8$-RISC-V (may work with your pi)

Wed Feb 20, 2019 9:43 am

hippy,

Interesting, what kind of processors have you been building? Good old boards covered in TTL?

I have some time day dreamed about doing that kind of thing. Apart from the complexity of the hardware I balked at not having software tools for the resulting architecture.

Nearly went for it when I discovered the stack based ZPU architecture had a GCC ready to go: https://en.wikipedia.org/wiki/ZPU_(microprocessor) but I ended up simply writing a ZPU emulator for the Parallax Propeller.

Aside: I find it amazing that wikipedia cites me in that artice, just after John Hennesy, Davide Patterson and , Krste Asanovic, all famous pioneers in Computer Science!

Then I contemplated a single instruction architecture. Specifically the "subleq": https://esolangs.org/wiki/subleq for which a C language like compiler is available.

But then came RISC V and FPGA...

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