mic_s
Posts: 78
Joined: Sun Oct 26, 2014 4:15 pm

Design your own 8$-RISC-V (may work with your pi)

Sat Oct 13, 2018 7:04 pm

If you are interrested to design your own RISC-V-Microprocessor / program in verilog, VHDL / this may be for you (the smallest FPGA-Harrdware-development system is available for 8$)

details:
https://riscv.org/2018contest/
( win up to USD $6,000, hurry up )
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Heater
Posts: 9957
Joined: Tue Jul 17, 2012 3:02 pm

Re: Design your own 8$-RISC-V (may work with your pi)

Sat Oct 13, 2018 8:11 pm

I started my own RISC-V implementation back in April. There is no way that it's going to be completed by the closing date of this competition.

https://github.com/ZiCog/sodor-spinal

Not that my humble effort would compete on speed, it has no pipelinning or caches etc. I'm sure someone could find a way to make a smaller design as well.

My humble effort is only intended as a way to get familiar with the RISC V ISA and learn how to design logic using the SpinalHDL hardware description language. http://spinalhdl.github.io/SpinalDoc/ To that end I'm keeping everything as simple as possible.

I don't see how anyone could create an entry to this competition in the time available, surely the winner will be an existing design adapted to the competition rules.

mic_s
Posts: 78
Joined: Sun Oct 26, 2014 4:15 pm

Re: Design your own 8$-RISC-V (may work with your pi)

Sat Oct 13, 2018 9:13 pm

You are right. This is not for the beginner. It is meant for the skilled Verilog/VHDL/FPGA-Programmer.
I don't see how anyone could create an entry to this competition in the time available, surely the winner will be an existing design adapted to the competition rules.

May be. … But there are also low hanging fruits: you can do your own RISC-V (Note: only Integer-Variant is required) in a few hundred Verilog LOC for a very, very small FPGA ( e.g. iCE40UP5K-SG48I )
Clifford and others demonstrated that:

http://www.clifford.at/
https://github.com/cliffordwolf/picorv32

Nice idee:
Design something like the mentioned minimal Integer-Risc-Vs as an add on for a Pi-Zero and do communication between Pi and your RISC-V via SMI or SPI. Your total Investment (beside your time) is 8 USD (UPDuinoBoard V1). Thats realy low cost.

mic

Heater
Posts: 9957
Joined: Tue Jul 17, 2012 3:02 pm

Re: Design your own 8$-RISC-V (may work with your pi)

Sat Oct 13, 2018 10:46 pm

I think the idea has lots of possibilities.

I got a picorv32 core running on DE-0 Nano board a year ago. https://github.com/ZiCog/xoro As I was new to Verilog I just cut out the picorv32 core and started surrounding it with my own memory and peripheral interfaces. Didn't take much time at all to get it running at 100MHz and communication via my home made UART module.

I was thinking to get it running on a cheap Lattice board as a peripheral chip. But then I got diverted by the idea of creating my very own RISC V core from scratch in SpinalHDL. Creating ones own processor is something every self respecting nerd should do, right? See sodor-spinal link above.

The thing about the competition is that even if you are skilled at Verilog I get the feeling that creating a new processor core from scratch is going to take more time than is available.

My completed sodor core runs to 870 lines of Spinal source code. Could have been about 600 had I been less verbose but I wanted it to be very clear to read. It would generate the same amount of logic in the end. Anyway, judging by the commit log in my github repository that core took me about 13 days.

The picorv32 core runs to 2000 lines of Verilog.

The idea of connecting an FPGA to the SMI is interesting...

fanoush
Posts: 372
Joined: Mon Feb 27, 2012 2:37 pm

Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 6:13 am

Heater wrote:
Sat Oct 13, 2018 10:46 pm
The thing about the competition is that even if you are skilled at Verilog I get the feeling that creating a new processor core from scratch is going to take more time than is available.
Google for DarkRisc-V, the author claims to do it from scratch over one night.

Heater
Posts: 9957
Joined: Tue Jul 17, 2012 3:02 pm

Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 6:52 am

fanoush,

Thanks for the heads up on darkriscv.

Wait a minute, a bit of exaggeration going on there, darklife does go on to say

"after weeks of exciting sleepless nights of work...the darkriscv reached a very good quality result, in a way that the "hello world" compiled by the standard riscv-elf-gcc is working fine! :)"

and

"The general concept is based in my other early RISC processors..."

The github commit history shows a lot more than a nights work.

Having said that, darkriscv sounds cool and pretty impressive. I might borrow some of his ideas for my effort :)

The more the merrier I say. It will be an interesting competition.

mic_s
Posts: 78
Joined: Sun Oct 26, 2014 4:15 pm

Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 1:11 pm

Number of Verilog-LOC for a rv32I-core ?

Interesting question. The mentioned darkriscV-core is 360 LOC ( Note: darkrisc dos't implement all Integer-Instructions yet … there are errors ... work in progress … i'm not envolved but it looks like darkrisc is a moving target … so final there will be a little bit more LOC )
Anyway, it is possible to implement a basic Risk-V rv32I-core (must pass the RISC-V RV32I compliance tests) with a few hundreds LOC.

If anyone is interested in the contest … read the instructions (https://riscv.org/2018contest/) carefully - Especially the paragraph „Minimum Requirements“ … Think about it ... Read it a second time … depending on your knowlage ... may be some Zeyphr-RTOS-learning is required.

I'm not allowed to participate but here are my hints:

(1) Try to design your very basic risc-V for the “smallest implementation” category. Do this for the Lattice 5K 4-input LUT „iCE40 Ultra Plus“ AND for the Microsemi IGLOO2 M2GL025 or SmartFusion2 M2S025. This way you double your points.

(2) In a second step, you may design an optional "Extra" (SMI-slave-interface, Low-Pin-Count-controller for external memory, ... ). May be this will bring you extra points.

Good luck.

and ... have fun with Verilog, FPGA and risc-V

.

Heater
Posts: 9957
Joined: Tue Jul 17, 2012 3:02 pm

Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 4:21 pm

I'm not sure we should worry about LOC so much. It's FPGA usage that matters at the end of the day. My RISC V core source code is kind of verbose, in order to make it clear to the human reader, but it all boils down to nothing when synthesized. I'm very sure these compilers do a better job of minimizing logic than I can. Unless I'm ordering up a ton of pipeline registers and such.

Especially if one is using a higher level language like Chisel or Spinal. That is like comparing lines of code between assembler language and C++.

I'm curious, why are you not allowed to participate? Are you connected to the competition organizers or restricted by your employers NDA's or what?

You are right, the competition instructions are tough. I don't have time to mess with some OS I have never heard of. I don't even want an OS in my creations.

hippy
Posts: 3880
Joined: Fri Sep 09, 2011 10:34 pm
Location: UK

Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 5:06 pm

mic_s wrote:
Sat Oct 13, 2018 9:13 pm
Your total Investment (beside your time) is 8 USD (UPDuinoBoard V1). Thats realy low cost.
I have always wanted to get into FPGA's but boards have historically been quite expensive, even prohibitively expensive, for someone who just wants to earn the 'done that' T-shirt.

I have crafted quite a few designs for very simply microcontroller cores over the years and have always wanted to turn at least one into actual silicon. I think I know what I'd like my next adventure to be. Time to see what tools are available for development on a Pi.

I'm guessing the $13.99 version 2.0 board with a USB programming connector would be the best choice if also looking at developing on a PC ?

fanoush
Posts: 372
Joined: Mon Feb 27, 2012 2:37 pm

Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 6:56 pm

hippy wrote:
Sun Oct 14, 2018 5:06 pm
I'm guessing the $13.99 version 2.0 board with a USB programming connector would be the best choice if also looking at developing on a PC ?
Yes, also the 1.0 version is missing few capacitors for stability and GND line is very thin, some people call the design horrible. The 2.0 version is improved after some feedback. And ftdi chip makes it easier. Definitely go for 2.0 unless you want cheapest and smallest and are prepared to flash it over SPI and possibly also add 1, 2 or 3 smd capacitors yourself.

BTW, This was first time I soldered SMD parts. I was very happy it worked but I prefer to avoid such adventure next time. Here is my result
upduino1caps.jpg
upduino1caps.jpg (45.95 KiB) Viewed 793 times
the third one is on second voltage regulator on the other side of the board.
Last edited by fanoush on Sun Oct 14, 2018 7:33 pm, edited 1 time in total.

mic_s
Posts: 78
Joined: Sun Oct 26, 2014 4:15 pm

Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 7:23 pm

I'm guessing the $13.99 version 2.0 board with a USB programming connector would be the best choice if also looking at developing on a PC ?
Yes.
I'm not sure we should worry about LOC so much. It's FPGA usage that matters at the end of the day.
You are right. But a low number of the required LOC (Verilog or SpinalHDL or ...) for your rv32i-core is a measure for „doable“ in a short time frame.
it all boils down to nothing when synthesized. I'm very sure these compilers do a better job of minimizing logic than I can.
YES … and no. (note the upper and lower case)
YES, generally it will do a fine job.
No, when it comes to the details: e.g. current tools have a lot of problems with border-crossing (e.g. two or more clock-domains) or with PLLs or …
I don't have time to mess with some OS I have never heard of. I don't even want an OS in my creations.
Take it as an additional chance to learn new things. BTW: Zyphyr isn't rocket science, If your core pass the RISC-V RV32I compliance tests, there will be no problem at all: It will do zyphyr by design. The two examples („Philosophers“, „Synchronization“) mentioned in the description are real small examples (think of it as „Hello World“ examples). They are chosen, so the intern mem of small FPGAs will hold the code.

.

fanoush
Posts: 372
Joined: Mon Feb 27, 2012 2:37 pm

Re: Design your own 8$-RISC-V (may work with your pi)

Sun Oct 14, 2018 8:44 pm

hippy wrote:
Sun Oct 14, 2018 5:06 pm
Time to see what tools are available for development on a Pi.
When I got upduino 1.0 I have rebuilt IceStorm toolchain with yosys, arachne-pnr directly on the Pi3. It run over night but finished successfully after many hours (with rootfs on ssd over USB). Later I also manged to rebuild riscv gcc toolchain and micropython https://github.com/mmicko/micropython/t ... s/picorv32 on the Pi3. I did it on the pi primarily because of easier SPI flashing. With 2.0 upduino version I'd probably go with linux PC as building geverything on pi is a bit slow and also the synthesis is cpu intensive. However it is definitely doable just with the Pi.

I did not try newer yosys/nextpnr/trellis tool set yet. It supports also much faster ECP5 lattice FPGA family. The Ultraplus family is low power, low price, low performance - good enough, but nontrivial designs top at 24-30Mhz max (which is still plenty for learning and lot of real stuff).

Heater
Posts: 9957
Joined: Tue Jul 17, 2012 3:02 pm

Re: Design your own 8$-RISC-V (may work with your pi)

Mon Oct 15, 2018 2:39 am

mic_s,
a low number of the required LOC (Verilog or SpinalHDL or ...) for your rv32i-core is a measure for „doable“ in a short time frame.
Quite so. I'm really liking SpinalHDL as it is so much nicer to be able to design logic in a nice readable, expressive, high level language than Verilog or VHDL. One neat thing is that Spinal compiles down to Verilog and one can easily see how much code one is generating.
...current tools have a lot of problems with border-crossing (e.g. two or more clock-domains) or with PLLs o
Multiple clock domains and PLL's are problems I have yet to tackle. Thanks I'll keep an eye out for that if/when I get there.
Take it as an additional chance to learn new things.
Ah yes. I'm up for that.

Thing is, having had to learn and use a new programming language and/or operating system every two years for forty years I got a bit jaded about it all. That might be a bit of an exaggeration, I'm not about to count them all. The prospect of having to become familiar with yet another f..ing language/OS to get something done starts to seem like a chore. A change without a difference. So much so that I kind of promised myself I'd never consider learning a new language again for what remains of my life.

But then I got curious about FPGA, logic design, CPU design...Especially as they are now readily available and so cheap and especially now that we have Open Source tools. Discovering that we don't need to fight with those huge, bloated, complex, slow, development tools from the FPGA vendors to get started was an eye opener. So much easier to kick around with Icarus and the Verilator. And of course the arrival of the RISC V is a great incentive to delve into this world.

So this last year has called for learning yet another f..ing language. In fact two of them, Verilog and Scala (SpinalHDL). Which has actually been quite a blast as what one is doing there when putting logic together is rather different to typical sequential programming. One has to think a bit differently.

So, things like Zyphyr are not off my table exactly, it's just that I'm not seeing the "shiny" in there to attract my attention yet.

mic_s
Posts: 78
Joined: Sun Oct 26, 2014 4:15 pm

Re: Design your own 8$-RISC-V (may work with your pi)

Mon Oct 29, 2018 9:10 am

fanoush wrote: When I got upduino 1.0 I have rebuilt IceStorm toolchain with yosys, arachne-pnr directly on the Pi3. It run over night but finished successfully after many hours (with rootfs on ssd over USB)
heater wrote: But then I got curious about FPGA, logic design, CPU design...Especially as they are now readily available and so cheap and especially now that we have Open Source tools. Discovering that we don't need to fight with those huge, bloated, complex, slow, development tools from the FPGA vendors to get started was an eye opener. So much easier to kick around with Icarus and the Verilator.
If anyone is interested in FPGA and want to test a real low-cost one, upduino 1 or 2 is an option. Concerning development tools the mentioned Open Source is another option. BTW. : Lattice as released a new ide, called Radon : Verilog/VHDL with Synplify Pro or LSE, Reveal, Aldec Active-HDL etc. … - its Diamond like. It works with Upduino. One-year-license is free.
.

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