morganwalper
Posts: 2
Joined: Thu Aug 24, 2017 9:01 pm
Contact: Website

Problem working with JK Flip Flop

Sun Dec 10, 2017 6:01 pm

Hello,
I'm trying to simulate a 2 binary counter using JK Flip Flop but is is not working. I tried another way such as testing two JK Flip Flop with individual clock (clock 1 and clock 2) and LED (LED 1 and LED 2). When clock 1 is ON, clock 2 is OFF, LED 1 and LED 2 is on. I've been working from the week to solve the problem but it ain't working.
Please, help me. :roll:
Thanks.

drgeoff
Posts: 7891
Joined: Wed Jan 25, 2012 6:39 pm

Re: Problem working with JK Flip Flop

Sun Dec 10, 2017 6:14 pm

As we have no idea how you are doing the simulation and no idea what you mean by "It's not working", how do expect anyone to help you?

And what is the relevance to Raspberry Pi which makes you think this is a good place to ask?

Heater
Posts: 8887
Joined: Tue Jul 17, 2012 3:02 pm

Re: Problem working with JK Flip Flop

Sun Dec 10, 2017 7:00 pm

I don't know. But if anyone wants to simulate a J-K Flip Flop on the Pi in Python or whatever language they choose I think that is great.

When I was about 13 I discovered a description of the J-K Flip Flop in a book on Digital Circuit Design. Including a schematic of one built out of NAND gates. I thought it was the most magical thing ever. It's has memory. It can count. Wow! These dumb logic gates can be smarter than I ever thought. That was fifty years ago mind. And the circuit is a beautiful thing of symmetry that takes a while to get your head around.

At the end of the day it's a simple program. Three inputs of 1 or 0. J, K and CLK. Two outputs of 1 or 0, Q and ~Q. And an internal state of 1 or 0. Call it S.

You can take the high level approach and just compute the required output for any input. Can probably be done with a look up table / state machine.

But that is cheating. I would take the low level approach...

A J-K Flip Flop can be built out of a bunch of NAND or NOR gates. So first write routines that can simulate those. How easy could that be?

Then connect up a bunch of your simulated NAND/NOR gates into a J-K Flip Flop.

For that you will need to have a schematic of a J-K Flip Flop. And understand it: For example: http://www.electronics-tutorials.ws/seq ... seq_2.html

I like the Master-Slave J-K Flip Flop as shown here: http://hyperphysics.phy-astr.gsu.edu/hb ... pflop.html

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