I'd like to know if this is an unfixed bug or if I'm just doing something silly (again).
The microchip datasheet indicates that write cycles for 24Cxx chips take 4mS to complete and during this time there will be no ack on the bus.
A quote from the datasheet:
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then
proceed with the next Read or Write command.
Could this be the cause of your problem?