Probably best to look at the sources in the linux kernel
https://github.com/raspberrypi/linux/bl ... 2835_smi.c
Not sure, but I think that document has never been officially released by Broadcom. Which makes publishing it problematic for us.fanoush wrote: ↑Mon Oct 01, 2018 11:42 amThanks a lot but that's not the point.
The point is that there is this 15 page PDF I have here, which may be more readable and helpful to people not fluent in linux kernel C code, and it got lost somewhere. So what happened with the pull request Gert mentioned? Is there something wrong with the pdf? Can I upload it somewhere?
I also found it being referenced here https://ultibo.org/forum/viewtopic.php?t=538#p5967 but the link does not work of course since gert removed his documentation fork.
Code: Select all
#define BCM2708_PERI_BASE 0x20000000
Code: Select all
#define BCM2708_PERI_BASE 0x3F000000
Code: Select all
. for (TestCount=0; TestCount<10000000; TestCount++)
{
if (smi_direct_write(0, TestCount, 0)==0)
{
fprintf (stderr, "smi_direct_write timed out...\n");
}
}
BEB wrote: ↑Mon Oct 28, 2019 8:50 pmAfter some problems, I have been able to compile the original source code from Gert on my 3B+.
First of all, I have found an issue in the original code which prevents it to run on the 3B+must be replaced byCode: Select all
#define BCM2708_PERI_BASE 0x20000000
to work on the 3B+Code: Select all
#define BCM2708_PERI_BASE 0x3F000000
Following codeshows a transfer rate of 1.5MB/s (for an 8 bits bus, so double if setup_smi() uses SMI_RW_WID16)Code: Select all
. for (TestCount=0; TestCount<10000000; TestCount++) { if (smi_direct_write(0, TestCount, 0)==0) { fprintf (stderr, "smi_direct_write timed out...\n"); } }
smi_write_block() and smi_read_block() functions provide better data rate, as bytes are transferred in bursts with exact timing programmed in setup_smi(). With 168ns for nWE pulse width, 168ns for nWE HOLD and 72ns for nWE SETUP, this gives a data rate of 2.4MB/s during bursts (I see an idle period of around 1 us between each call, coming from the preparation code in the function.
I have checked that nWE and nCS are exactly the same as programmed in the timing register, so I think it can be safely expected that higher data rates can be achieved with narrower pulses (168ns is quite a large value for modern components. Smaller values can be used safely with 3.3V FPGA)