It is a CPU bus with read and write transactions. Thus always a master.Can this SMI be also used to connect two Pis and have bidirectional fast data transfer between them?
Thanks a lot!
Well it would make sense only if it is relatively cheap and easy. Sticking $5 zero on top of $35 pi3 to get fast swap space may make sense. If the cost is much higher it may not be practical. BTW, few weeks ago I found cheap $8 FPGA board http://gnarlygrey.atspace.cc/developmen ... ml#upduino that could be useful for such stuff and does not cost arm and leg. I hope I can learn some FPGA basics with this board and possibly interface it with the Pi in some interesting ways.Gert van Loo wrote: ↑Tue Nov 21, 2017 10:47 amTo simplest way to exchange information between Pi's using SMI would be a dual-ported
16 bit wide memory which is read and written from both sides or two FIFOs.
I have to look into that but what I recall it would need some logic. Maybe a small FPGA with
lots of internal (or external) memory would be required. If somebody is interested I
see if i can spend some time on that.
The CPLD was 'just in case'. The current code works without it. (Although maybe it is needed after all to get the DMA sorted out)Looks like you are using CPLD in the schematics so the IDE interface cannot be driven directly by SMI?
I had a look and the SMI offers at least 16 wide data bus with 5 bit address bus.16 bit wide memory which is read and written from both sides or two FIFOs.
I have to look into that but what I recall it would need some logic.
Code: Select all
#define SMI_RW_MODE68 0x00800000 // Run cycle motorola mode #define SMI_RW_MODE80 0x00000000 // Run cycle intel mode
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#define SMI_RW_WID8 0x00000000 // Data width 8 bits
Uhhh.... I have given up on this, that is why started this thread.I am looking forward to see how far you get with this.
It has been on Github for three years! You can hardly calling that 'keeping it a secret'Keeping that 128 I/O secret?
Can't remember, I don't think there is an ALT mode for that. It must have been a normal GPIO.IRQPn on gpio27?
At the time I wrote that code, I had access to the documentation.I was looking into doing the same thing, and have been trying to get actual register level documentation from RPF, Broadcom reps etc - no joy.
It uses the 23017 I2C expander, which has 3 address bits and 16 I/O which gives 8x16=128 I/O bits.128 on one i2c is good, as long at it is not a Pi2 or 3, i2c0 can be used to get 256 I/O
Now we know who to blameI don't understand why they keep the SMI a secret. The only reason why it is not in the published documentation is because I left it out.
100MB-150MB/sec would still be sweet
Hindsight is great I suspect Bill Gates now regrets saying that.Gert van Loo wrote: ↑Wed Nov 22, 2017 5:45 amAt the time I wrote that code, I had access to the documentation.
I don't understand why they keep the SMI a secret. The only reason why it is not in the published documentation is because I left it out.
At the time it was no use because there was no way you could get it working on a Pi with the 26 pin header.
Learned another lessen, I fell into the '640K ought to be enough for anybody' trap.
I'm no hardware guy, but isn't Compact Flash very close to a 40-pin IDE interface? Some of them can be pretty fast.
Wow I had forgotten that, I have used 64MB CF card for a FreeDOS CNC PC with a IDE to CF adapter which only had a few things on it.I'm no hardware guy, but isn't Compact Flash very close to a 40-pin IDE interface?
I have just created a stand-alone version of the SMI specs.
It is. One could buy CF to IDE cable adapters, some embedded boards contained IDE buses with CF sockets, and there were even a couple of CF cards with IDE micro-HDD embedded within them.
Gert, what a tease you areI have just created a stand-alone version of the SMI specs.
No, as I said there is nothing special about the SMI.Any patented stuff?
Hi Gert, feel free to release the documentation.Gert van Loo wrote: ↑Mon Nov 27, 2017 9:36 amNo, as I said there is nothing special about the SMI.Any patented stuff?
For those interested a bit of history: The first Raspberry-Pi 2835 was originally a 2708.
The 2708 was the same die in a different package which had two 128Mbyte stacked SDRAM chips inside.
However there also was a 2707, the predecessor. A LOT of work was done to the 2707 to get to the 2708.
The GPU was made more powerful, the 3D engine was completely new, the ISP was improved
new peripherals (e.g. SLIM bus) and a lot more like the approval we got to add an ARM core.
The SMI however was the same as the chip BEFORE the 2707 and I think even the one before that.
A such I regard the SMI as old fashioned proven technology. Also there is little you can patent on the
old 8080/6800 bus cycles from the 1970's.
I know TI had a interface which could run 80/68 cycles, but was so infinitely programmable you could even talk to SDRAM with it.
I got the PDF from your fork previously and I still have it. Now I wanted to point someone to public source for this pdf but I can't find it anywhere. The fork is gone and I can't find this "Secondary Memory Interface.pdf" anywhere. I guess it should be somewhere below https://github.com/raspberrypi/document ... aspberrypi but no luck finding it.
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