I know it is a limitation of the clock, but what is it derived from, for example sdcard clock is derived from core clock integer divisions.
And if iirc for the DAC pin 12 35 and 40 all 4 are pwm signals that will be used(well not necessarily pure pwm mode but it is a fast variable signal), with 12 being clock for actual sample rate*bit rate*channels(?), 35 being a clock for knowing which channel is being processed at the moment, and 40 containing actual raw pwm data.
It just doesn't add up in my head, because I can't figure out a way where you can integer divide a core clock into 192khz 2 channel 24bit signal,
I am just wondering if core clock switch change can be performed like with sdcard overclocking to get access to different sample rates etc.
Although I might be wrong, because I don't know how PCM signal actually works on the internal side of things and perhaps it would get real messy to get it right
I remember that FS signal was Channel Control signal for switching which channel is being transmitted and CLK is "pacing" clock for DOUT ; DIN is for ADCs