kubast2
Posts: 1
Joined: Fri Mar 13, 2020 5:47 pm

What's the reason for 24/192 khz limitation for pcm output?

Sun Apr 26, 2020 3:48 pm

I know it is a limitation of the clock, but what is it derived from, for example sdcard clock is derived from core clock integer divisions.

And if iirc for the DAC pin 12 35 and 40 all 4 are pwm signals that will be used(well not necessarily pure pwm mode but it is a fast variable signal), with 12 being clock for actual sample rate*bit rate*channels(?), 35 being a clock for knowing which channel is being processed at the moment, and 40 containing actual raw pwm data.
It just doesn't add up in my head, because I can't figure out a way where you can integer divide a core clock into 192khz 2 channel 24bit signal,
I am just wondering if core clock switch change can be performed like with sdcard overclocking to get access to different sample rates etc.

Although I might be wrong, because I don't know how PCM signal actually works on the internal side of things and perhaps it would get real messy to get it right
https://pinout.xyz/pinout/pcm#
I remember that FS signal was Channel Control signal for switching which channel is being transmitted and CLK is "pacing" clock for DOUT ; DIN is for ADCs

HiassofT
Posts: 282
Joined: Fri Jun 30, 2017 10:07 pm
Location: Salzburg, Austria
Contact: Website

Re: What's the reason for 24/192 khz limitation for pcm output?

Sun Apr 26, 2020 9:32 pm

The limit is actually 384kHz/32bit at 2 channels, Eric Anholt confirmed that the docs state a maximum bclk of 25MHz.

There are no clock sources inside the RPi that are suitable to derive audio clock rates with an integer divisor (except 19.2MHz OSC on RPi0-3 which is fine for 8kHz and 16kHz at 24bit), so the PCM clocked is usually derived from plld_per (500MHz on RPi0-3, 750MHz on RPi4) using a fractional divider.

While fractional dividers aren't perfect (they alter between N and N+1 cycles) they are in general good enough as the base clock is high enough (so jitter is in the 1.3-2ns range).

If you need/want better audio clocks then the solution is to use external oscillators/clock generators and let the I2S block run in slave mode (external clocking). Several sound cards do this to get cleaner clocks.

so long,

Hias

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