kondaveetiarungopal
Posts: 69
Joined: Fri Apr 26, 2013 6:35 am

DMA and IOMMU and SMMU for SPI

Thu Oct 04, 2018 5:43 am

Hi,
I want to Transfer the data from spi to lcd module and vice versa.
1) how the IOMMU will convert the virtual to physicle and virtual to bus addresses in linux kernel.
2)During DMA i want to disable L2 Cache.Is There Any Possibility to Disable the L2 Cache.or Is there Any DMA APis to disable the L2 Cache.
3)Raspberry Pi contains the SMMU Chip in Built?
4)How Raspberry Pi converts virtual to Physicle Address in linux kernel?how can i change MMU Chip Options.

kondaveetiarungopal
Posts: 69
Joined: Fri Apr 26, 2013 6:35 am

Re: DMA and IOMMU and SMMU for SPI

Thu Oct 04, 2018 10:15 am

Please give some Valubla Reply.

6by9
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
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Re: DMA and IOMMU and SMMU for SPI

Thu Oct 04, 2018 12:29 pm

You waited all of 4.5 hours before pinging the thread - please have some patience!

1) There is no IOMMU on the Pi. The DMA controller always gets programmed with physical addresses.
2) IIRC DMA operations normally do bypass the caches, having first ensured that they have been flushed/invalidated before doing the transfers. What is your specific need to bypass the L2 cache?
3) The ARM cores have an MMU. Yes that is built in to the SoC.
4) Standard Linux MMU management. Messing with it sounds like a good way to bork the system.

DMA documentation is all in the kernel tree:
https://github.com/raspberrypi/linux/bl ... MA-API.txt
https://github.com/raspberrypi/linux/bl ... -HOWTO.txt
https://github.com/raspberrypi/linux/bl ... ibutes.txt
Software Engineer at Raspberry Pi Trading. Views expressed are still personal views.
Please don't send PMs asking for support - use the forum.
I'm not interested in doing contracts for bespoke functionality - please don't ask.

kondaveetiarungopal
Posts: 69
Joined: Fri Apr 26, 2013 6:35 am

Re: DMA and IOMMU and SMMU for SPI

Mon Oct 08, 2018 7:38 am

HI,
Thank you for your Reply.
iam working on tft lcd interfacing to spi controller.so here communication is spi.
so here iam using DMA communication for spi transfer.so during transfer of DMA i need to transfer data to directly to ram.
not sync with the caches.every time i need to write the fresh data to ram.instead of flushing l2 cache.



2)During Boot time why we need to disable the l2cache?is there any particular reason for disabling that one.

3)is there any possibility to boot a kernel image from 2nd cpu instead of first cpu.





Reg,
K.arungopal

6by9
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
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Re: DMA and IOMMU and SMMU for SPI

Mon Oct 08, 2018 9:22 am

kondaveetiarungopal wrote:
Mon Oct 08, 2018 7:38 am
iam working on tft lcd interfacing to spi controller.so here communication is spi.
so here iam using DMA communication for spi transfer.so during transfer of DMA i need to transfer data to directly to ram.
not sync with the caches.every time i need to write the fresh data to ram.instead of flushing l2 cache.
SPI display support is fairly standard. Unless you have some very good reasons not to, then work with the kernel frameworks rather than inventing your own.
A cache flush is generally more efficient as it will be doing big writes to memory instead of many small and inefficient ones.
It is possible to map memory into userspace bypassing the cache, but the real uses cases are fairly rare.
kondaveetiarungopal wrote:2)During Boot time why we need to disable the l2cache?is there any particular reason for disabling that one.
???
If you are referencing the config.txt / "vcgencmd get_config int" option of "disable_l2cache" then it's not doing what you are thinking it does.
https://www.raspberrypi.org/documentati ... /memory.md
Setting this to 1 disables the CPU's access to the GPU's L2 cache, and requires a corresponding L2 disabled kernel. Default value is 0.
(Minor correction needed on that - the default on a Pi 2 (BCM2836) or 3 (BCM2837) is 1, whilst on Pi 0/1 (BCM2835) is 0.)
Note that that is the GPU's L2 cache. On 2836/7 the ARMs have their own L2 cache, therefore there is a performance hit by feeding all the ARM accesses through the GPUs L2 cache as well (it'll evict stuff that the GPU wants).
kondaveetiarungopal wrote:3)is there any possibility to boot a kernel image from 2nd cpu instead of first cpu.
Many things are possible, but often the thought processes behind that desire are erroneous.

Why try to move the kernel rather than isolate the 2nd (or 3rd or 4th) cpu for your purposes?
It's a chicken and egg situation - you'd normally specify this on the Linux command-line, so which CPU has done the parsing of the command line to find that you want to reserve the 1st core? If anything has set up interrupt routines then those have to be moved too.

isolcpu allows you to remove a CPU from the scheduler, and you can then manually schedule your processes to those isolated cores.
Alternatively if you look in the device tree setup for BCM2836/2837then you can knock out complete CPUs. However if you've done that then nothing can run on it as AIUI the MMU is common between all ARM CPU cores. A CPU with no memory is of limited use.
Software Engineer at Raspberry Pi Trading. Views expressed are still personal views.
Please don't send PMs asking for support - use the forum.
I'm not interested in doing contracts for bespoke functionality - please don't ask.

kondaveetiarungopal
Posts: 69
Joined: Fri Apr 26, 2013 6:35 am

Re: DMA and IOMMU and SMMU for SPI

Wed Oct 24, 2018 11:01 am

Hi Thank you for your reply.

please give some valuable reply.
Hi,
I am working on a raspberry pi 3.i have doubt regarding timers.
1)can you Please tell me the difference between the cpu local timers and watchdog timers.
2)if cpu in idle mode then the how the jiffies variable is incremented?
3)how the jiffies variable is incremented in the per cpu?when you see cat /proc/interrupts weather it indicated the jiffies count?
4)how to access jiffies timer in raspberry pi?
5)how to access per cpu local timer?
6)if i write a sample module using mod_timer then this timer will handled by cpu local timer or jiffies timer?

can you Please tell me above doubts

6by9
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 5805
Joined: Wed Dec 04, 2013 11:27 am
Location: ZZ9 Plural Z Alpha, aka just outside Cambridge.

Re: DMA and IOMMU and SMMU for SPI

Wed Oct 24, 2018 12:33 pm

kondaveetiarungopal wrote:
Wed Oct 24, 2018 11:01 am
Hi Thank you for your reply.

please give some valuable reply.
Hi,
I am working on a raspberry pi 3.i have doubt regarding timers.
1)can you Please tell me the difference between the cpu local timers and watchdog timers.
2)if cpu in idle mode then the how the jiffies variable is incremented?
3)how the jiffies variable is incremented in the per cpu?when you see cat /proc/interrupts weather it indicated the jiffies count?
4)how to access jiffies timer in raspberry pi?
5)how to access per cpu local timer?
6)if i write a sample module using mod_timer then this timer will handled by cpu local timer or jiffies timer?

can you Please tell me above doubts
Your post was deleted the first time because it was a duplicate of viewtopic.php?f=44&t=225353&p=1383463, and you've now reposted exactly the same duplicate.
Please do not double post - it wastes peoples time. And now I'll ask the mods to lock this thread.
Software Engineer at Raspberry Pi Trading. Views expressed are still personal views.
Please don't send PMs asking for support - use the forum.
I'm not interested in doing contracts for bespoke functionality - please don't ask.

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