julyjim
Posts: 117
Joined: Tue Jan 31, 2017 5:04 am

SPI with C/D ?

Wed Apr 25, 2018 9:20 pm

I have rather odd TFT display I am using to learn how to code SPI.

According to "standard" SPI I need 4 wires for interface to RPi.

Now the "standard" naming seems to be eluding some vendors.
I can relate standard /SS to /CS - useful to enable more devices on single SPI bus

MOSI
MISO
is a different story , but vendors naming convention likes DIN DOUT can be decoded

SCLK
Clock and its naming can also be decoded from datasheet.

Now
why does SPI / TFT display hardware has "C/D" pin beats me.
(The TFT pins are on separate SPI bus, so is SD.)

Any suggestions?

PS I am deliberately avoiding any vendors "part number / module designation."

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DougieLawson
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Re: SPI with C/D ?

Wed Apr 25, 2018 10:26 pm

The C/D pin is command or data to effectively extend the data on the bus from 8 bits to nine.
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mark3112
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Re: SPI with C/D ?

Thu Apr 26, 2018 6:07 pm

MOSI – Master Out Slave In
MISO – Master In Slave Out
Depends on who’s Master and who’s Slave.
Using a pi, thats the master, and your TFT is the Slave, unless there is a pi slave option I'm not aware of.
You can make a real CPU in a FPGA, but you can’t make a real FPGA in a CPU.

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