RoboTrader
Posts: 8
Joined: Mon Nov 13, 2017 1:53 pm

Why this GPIO-sequence and which GPIOs for Interfaces?

Sat Jan 06, 2018 1:29 pm

Hello in a great programming New Year!

I have two questions:

1: The more philosophical question:
Why the pins are in order like they are? Why they do not build it with 2 Pins on one side with 5V, 3.3V and GND, then all the programmable ones? Why this "chaos"? Is this because of the micro controller? Or why?

2: The knowledge question:
I read many different versions of which pins are used for SPI, for I2C, ... For me it would be great to "see" all the assignment in configuration files or anything like that on my Pi instead of "speculations". Or can I measure it at the pins myself?
Or do you have the official assignment of the pins for all the Interfaces?

Thanks a lot and a great weekend
RoboTrader

HermannSW
Posts: 612
Joined: Fri Jul 22, 2016 9:09 pm

Re: Why this GPIO-sequence and which GPIOs for Interfaces?

Sat Jan 06, 2018 8:33 pm

--> Raspberry camera / gstreamer / raspivid / raspiraw (bookmark list):
https://stamm-wilbrandt.de/en/Raspberry_camera.html

https://github.com/Hermann-SW/raspiraw      https://github.com/Hermann-SW/userland      https://twitter.com/HermannSW

klricks
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Location: Grants Pass, OR, USA
Contact: Website

Re: Why this GPIO-sequence and which GPIOs for Interfaces?

Sun Jan 07, 2018 2:14 am

RoboTrader wrote:
Sat Jan 06, 2018 1:29 pm
Hello in a great programming New Year!

I have two questions:

1: The more philosophical question:
Why the pins are in order like they are? Why they do not build it with 2 Pins on one side with 5V, 3.3V and GND, then all the programmable ones? Why this "chaos"? Is this because of the micro controller? Or why?
The SOC chip is a BGA type with over 300 connection points. https://en.wikipedia.org/wiki/Ball_grid_array
The GPIO's available to the RPi user are a subset of the available GPIO's on the SOC.
See: https://elinux.org/RPi_BCM2835_Pinout

Notice that the GPIO's and other functions are dispersed on the grid array in a seemingly random order. For example: The serial UART pin TXD (GPIO 14) is at physical grid array location 4-D, and RXD (GPIO 15) is at grid array location 2-E on the SOC.
However on the RPi GPIO header they are placed next to each other Pin 8 & 10 with a convenient and necessary GND pin 6 next to them. Other pins with similar functions are grouped together as well eg SPI.
It is very difficult to route the traces (tracks) even with a 6 layer board that the RPi has and using automatic routing software. So I think the RPF did as well as possible with the layout that we now have.
RoboTrader wrote:
Sat Jan 06, 2018 1:29 pm
2: The knowledge question:
I read many different versions of which pins are used for SPI, for I2C, ... For me it would be great to "see" all the assignment in configuration files or anything like that on my Pi instead of "speculations". Or can I measure it at the pins myself?
Or do you have the official assignment of the pins for all the Interfaces?

Thanks a lot and a great weekend
RoboTrader
Not sure what you mean by "speculation"? The pinout has been pretty solid for a long time:

Here is a good reference: https://pinout.xyz/
You can also type pinout on the RPi at the command prompt.
Unless specified otherwise my response is based on the latest and fully updated Raspbian Stretch w/ Desktop OS.

RoboTrader
Posts: 8
Joined: Mon Nov 13, 2017 1:53 pm

Re: Why this GPIO-sequence and which GPIOs for Interfaces?

Sun Jan 14, 2018 8:53 am

Thanks for your answers!
It is very difficult to route the traces (tracks) even with a 6 layer board that the RPi has and using automatic routing software. So I think the RPF did as well as possible with the layout that we now have.
I'm sorry if it sounds like "I don't like it". I was just wandering for the (for me) chaos and interested in an explanation.
Not sure what you mean by "speculation"? The pinout has been pretty solid for a long time:
Two situations are real reasons for my doubts:
a) With the normal RPi.GPIO library in python I can use every pin as pwm. But always finding the explanation that this is just possible with pigpen or only 2 pins are available - sometimes only one.
b) I'm using all interfacing like I2C, 1-WIRE, SPI. Therefore I made a new pin graph for me with the "reservations" for the interfaces. So I used the (in my opinion) absolute free pins 5,6,13 and 12,25,26 for a L293D-project and there are displayed warnings.
Here is a good reference: https://pinout.xyz/
You can also type pinout on the RPi at the command prompt.
The link is the same I used for my "pin graph".
And "pinout" in the shell doesn't work ("Command not found"). Why?

I use the Raspbian Stretch Lite.
Last edited by RoboTrader on Sun Jan 14, 2018 3:39 pm, edited 1 time in total.

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joan
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Location: UK

Re: Why this GPIO-sequence and which GPIOs for Interfaces?

Sun Jan 14, 2018 1:13 pm

PWM is available on every GPIO if software timing of the pulses is used.

The Pi has several GPIO which can be configured in a PWM mode where internal hardware is used to time the pulses. The number of those GPIO brought out to the expansion header varies between 1 for the earliest Pi models, to 4 for models with the 40 pin expansion header, to 9 for the compute module.

To confuse the issue further there are modules such as my pigpio which can generate hardware timed PWM on GPIO 0-31 but with a restricted range of frequencies.

Daniel Gessel
Posts: 21
Joined: Sun Dec 03, 2017 1:47 am

Re: Why this GPIO-sequence and which GPIOs for Interfaces?

Sun Jan 14, 2018 9:45 pm

I could only find 3 pwm pins on https://pinout.xyz, two of which are labeled PWM0. Is there a more complete, if less pretty and easy to read, reference - short of going to schematics?

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joan
Posts: 13301
Joined: Thu Jul 05, 2012 5:09 pm
Location: UK

Re: Why this GPIO-sequence and which GPIOs for Interfaces?

Sun Jan 14, 2018 10:34 pm

Not really.

My table at http://abyz.me.uk/rpi/pigpio/cif.html#gpioHardwarePWM

Also the underlying source http://www.raspberrypi.org/documentatio ... herals.pdf

Page 102 from my memory.

Daniel Gessel
Posts: 21
Joined: Sun Dec 03, 2017 1:47 am

Re: Why this GPIO-sequence and which GPIOs for Interfaces?

Mon Jan 15, 2018 3:02 pm

So there are two PWM channels that are brought out to up to 4 pins. Then there’s using the dma engine, If I understand correctly, which can work for all GPIO pins. Finally, there’s SW PWM, which can be implemented with busy loops, real time clock checks, even Nano sleeps if you can live with variability. It seems like there ought to be a way to use the clock interrupts to handle pwm - but only for someone who’s already using bare metal or who’s intimate with kernel hacking.

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