rhary
Posts: 1
Joined: Thu Oct 05, 2017 1:59 pm

Multiple I2S ports on RPi 3

Thu Oct 05, 2017 2:25 pm

Hello Everybody,

I'm new in this forum and I'm coming with relatively specific question.

For my project I need to connect multiple (more than 2) I2S microphones to RPi 3. I see several different ways how to do that, on the other hand I'd like stay with minimum (or none) additional hardware.

My idea is to use standard existing I2S, just to add additional data-in ports on the GPIO. All I2S clocks would be shared over all I2S ports. Like that I'd read from GPIO instead of one bit, four or more bits (following number of I2S data-in ports I'd add). I had several discussions and I received fairly contradictory informations as on one side it was told to me that GPIO is not fast enough, on the other one of posts in this forum speaks about GPIO speed on the level of MHz. My target speed (bitclock) is of order 700kbps.

Can anybody advise me if the approach I proposed is feasible, e.g. that in principle the HW can manage it, and also point out (if exist) some software (drivers) that could help me to implement such a multiport I2S input.

Thanks to everybody

Robert

piras77
Posts: 147
Joined: Mon Jun 13, 2016 11:39 am

Re: Multiple I2S ports on RPi 3

Thu Oct 05, 2017 7:36 pm

rhary wrote:
Thu Oct 05, 2017 2:25 pm
For my project I need to connect multiple (more than 2) I2S microphones to RPi 3. I see several different ways how to do that, on the other hand I'd like stay with minimum (or none) additional hardware.
The Pi supports an I2S peripheral. See §8 in the datasheet https://www.raspberrypi.org/app/uploads ... herals.pdf. The peripheral alone appears not to support more than 2 sources.
rhary wrote:
Thu Oct 05, 2017 2:25 pm
My idea is to use standard existing I2S, just to add additional data-in ports on the GPIO.
In order to sample data, it normally needs a clocked (hardware) (de)serializer which writes into a (hardware) FIFO (which in turn is read by tight software loops, by ISR or DMA). The number of those (de)serializers is limited (PCM, SPI0, SPI1).

You can read the GPIO pins directly, however not in a paced (clocked) mode. Hence you have no control over the time between two samples. viewtopic.php?f=44&t=191949&p=1210657#p1210655 There are ways to try to circumvent this (e.g. by sampling as fast as possible and taking a time stamp between each two samples; afterwards you single out the samples that match your needs).
rhary wrote:
Thu Oct 05, 2017 2:25 pm
All I2S clocks would be shared over all I2S ports. Like that I'd read from GPIO instead of one bit, four or more bits (following number of I2S data-in ports I'd add).
AFAIK, this kind of pacing (i.e. to read several GPIO pins at a certain clock speed) is not available.
rhary wrote:
Thu Oct 05, 2017 2:25 pm
My target speed (bitclock) is of order 700kbps.
To "sample" a GPIO bank (i.e. pin 0 to 31) at an _average_ clock speed of more than 700 k/s is possible (either in a tight loop on bare metal or with DMA). However, there is no guarantee that the minimum distance between two subsequent samples is at least 1s/700k.

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