I'd have to assume the answer is "yes," but is there anything in the SPI system that insures that simultaneous access to /dev/spidev0.0 and /dev/spidev0.1 wind up being properly interleaved rather than just step on each other? I have a potential use case where the two would be opened by separate programs and would not attempt to coordinate writes. Since the two chip selects are separate, it doesn't really matter what order writes are done in, just as long as the hardware doesn't get confused and try to do them both at the same time or interrupt a transfer in progress or anything silly like that.
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