Page 2 of 2

Re: GPIO max current

Posted: Thu Nov 02, 2017 2:48 pm
by piras77
6by9 wrote:
Thu Nov 02, 2017 1:03 pm
I suspect the 50mA isn't a hard limit enforced in the hardware, it's the point where you'll be creating issues.
Within the SoC you're routing power from balls underneath to each block. How big...
Since we don't know, it would be nice to get an explanation, preferably from Gert (since he posted here). Are there any other SOCs out there which are *comparable* and have a proper documentation? By now it appears to me the 50mA are more a wild guess than a limit. Probably there are no factory tests and no (hard) predictions. Maybe the manufacturers are afraid that people would take static limits for dynamic signals. Maybe the 50mA are really documented by Broadcom, but as so many other documents, they don't disclose them. I don't know. Since I was curious, I ran a Pi-2 for a while with something about 150mA (static) on Bank0, without visible damage (I would have tried more but ran out of resistors). I might have got lucky, or not. Who can say. If I have time, I'm going to load *safely* all 28 pins step-by-step to 16mA, verify voltage drop and heat, and post my findings. Up to now I didn't encounter any application that would need this, just curious.

Re: GPIO max current

Posted: Thu Nov 02, 2017 3:03 pm
by jamesh
piras77 wrote:
Thu Nov 02, 2017 2:48 pm
6by9 wrote:
Thu Nov 02, 2017 1:03 pm
I suspect the 50mA isn't a hard limit enforced in the hardware, it's the point where you'll be creating issues.
Within the SoC you're routing power from balls underneath to each block. How big...
Since we don't know, it would be nice to get an explanation, preferably from Gert (since he posted here). Are there any other SOCs out there which are *comparable* and have a proper documentation? By now it appears to me the 50mA are more a wild guess than a limit. Probably there are no factory tests and no (hard) predictions. Maybe the manufacturers are afraid that people would take static limits for dynamic signals. Maybe the 50mA are really documented by Broadcom, but as so many other documents, they don't disclose them. I don't know. Since I was curious, I ran a Pi-2 for a while with something about 150mA (static) on Bank0, without visible damage (I would have tried more but ran out of resistors). I might have got lucky, or not. Who can say. If I have time, I'm going to load *safely* all 28 pins step-by-step to 16mA, verify voltage drop and heat, and post my findings. Up to now I didn't encounter any application that would need this, just curious.
As stated above, Gert helped design the chip, and generally chip design doesn't involve wild guesswork. Of course, it can probably, unsafely, provide more than the specified amounts, as you have seen, but there may now be some damage internally, and you may have dramatically reduced the life of the chip. Anything that relies on producing more than the specified values is asking for trouble.

Re: GPIO max current

Posted: Thu Nov 02, 2017 3:32 pm
by piras77
jamesh wrote:
Thu Nov 02, 2017 3:03 pm
Anything that relies on producing more than the specified values is asking for trouble.
I agree. What I'm argue is about the specification itself which has not been disclosed. Since that ain't going to happen, a discussion about the specified values appears to be rather pointless. So what remains is the "recommendation" of various people (including people related to the RPF and Broadcom) not to go over 50mA per bank. And I have no doubt that is enough for most of the users here.

Re: GPIO max current

Posted: Thu Nov 02, 2017 3:34 pm
by jojopi
One thing I have always wondered: if some of the GPIOs are sourcing current and others are sinking, then does the 50mA limit apply to the sum of the absolute currents, or to the maximum of source and sink?

Re: GPIO max current

Posted: Thu Nov 02, 2017 4:03 pm
by jamesh
piras77 wrote:
Thu Nov 02, 2017 3:32 pm
jamesh wrote:
Thu Nov 02, 2017 3:03 pm
Anything that relies on producing more than the specified values is asking for trouble.
I agree. What I'm argue is about the specification itself which has not been disclosed. Since that ain't going to happen, a discussion about the specified values appears to be rather pointless. So what remains is the "recommendation" of various people (including people related to the RPF and Broadcom) not to go over 50mA per bank. And I have no doubt that is enough for most of the users here.
So what you are saying is that you trust a piece of paper more than the people involved with designing the chip? The specification is not the datasheet, it was the specification used to design the chip in the first place. That is clearly very much a confidential document at Broadcom. So since you are never going to see that document, I'd suggest simply believing the people who are intimately familiar with the chip itself. That should be enough for ALL users.

Re: GPIO max current

Posted: Thu Nov 02, 2017 4:11 pm
by piras77
jamesh wrote:
Thu Nov 02, 2017 4:03 pm
So what you are saying is that you trust a piece of paper more than the people involved with designing the chip?
I trust/believe in information that can be verified.
jamesh wrote:
Thu Nov 02, 2017 4:03 pm
I'd suggest simply believing the people who are intimately familiar with the chip itself. That should be enough for ALL users.
Which brings any discussion to a HALT.

Anyway, since the same topic pops up now and then, you may want to make it stick (there is a FAQ if I remember correctly.)

Re: GPIO max current

Posted: Thu Nov 02, 2017 9:17 pm
by jdb
jojopi wrote: One thing I have always wondered: if some of the GPIOs are sourcing current and others are sinking, then does the 50mA limit apply to the sum of the absolute currents, or to the maximum of source and sink?
It's a function of both.

If your GPIO pad is sourcing current, then it's effectively connecting VDDIO via a resistor to the GPIO. Similarly, if the GPIO is sinking current, then it's connecting VSSIO via resistor to the GPIO.

There are a set number of VDDIO and VSSIO pads connected to each GPIO bank. The number and dispersion of these determines how much aggregate current you can source/sink at any one time, as you have several factors to consider.

As said previously, the current must go via the package ball(s), through the in-package substrate (basically a little high-density PCB that mounts the silicon die), through the teensy bond wires and on to the chip.

There are also semiconductor effects with sourcing/sinking large amounts of current - the metal layers on the chip that transmit the current from the power pads to the GPIOs contribute to series resistance and as such there will be a voltage gradient across the row of GPIO pads. Too much voltage gradient and things start to get reverse biased, leak, overheat locally etc.

I would say that the 50mA global limit applies to simultaneous source and sink currents.

Also:
piras77 wrote: I trust/believe in information that can be verified.
You have someone who was on the design team of the chip in question stating facts about the design. You have multiple posters in this thread with extensive academic and professional qualifications related to chip design providing their informed opinions. What sort of verification are you expecting, if not words from the horse's mouth?

Re: GPIO max current

Posted: Thu Nov 02, 2017 11:50 pm
by Gert van Loo
Is the 50mA a hard number? NO! It is good design practice.
It depends on too may factors like:
- Quality of power supply
- Type of pin load (capacitive, resistive or inductive and amount of capacity/inductance)
- Quality of board routine
- Quality and amount plus placement of chip decoupling
- How many pins your switching and how fast.
- What else is running at that time.

The 'power supply will collapse' was for the Pi-1 which had very little spare current on the 3V3 supply.

Your dU of 500mV is also not the worst case.
You have a worse case working pad if the output voltage is 1.3V (Lowest level still seen as "high").
Thus a voltage drop of 3.3-1.3=2V at 50mA is 100mW.

(And yes the "me" was sort of a joke :lol: )

Re: GPIO max current

Posted: Fri Nov 03, 2017 12:30 am
by piras77
jdb wrote:
Thu Nov 02, 2017 9:17 pm
I would say that the 50mA global limit applies to simultaneous source and sink currents.
So, you don't think that the different levels of voltage drops for sink and source do not matter and do not effect the power dissipation.
jdb wrote:
Thu Nov 02, 2017 9:17 pm
You have someone who was on the design team of the chip in question stating facts about the design. You have multiple posters in this thread with extensive academic and professional qualifications related to chip design providing their informed opinions. What sort of verification are you expecting, if not words from the horse's mouth?
So what you say as an engineer: If enough people state something, it becomes true. Verification by others doesn't matter. Are you sure you've chosen the right profession? I believe that you believe in these people. But actually, that doesn't matter (and I honestly shouldn't need to explain that to you).

Thanks @ Gert and also 6by9 for trying to explain and for not preaching / not being condescending. I'd really had liked to follow up, but obviously things got out of hand.

Re: GPIO max current

Posted: Fri Nov 03, 2017 10:02 am
by jamesh
Had enough of this snark.