One thing I have always wondered: if some of the GPIOs are sourcing current and others are sinking, then does the 50mA limit apply to the sum of the absolute currents, or to the maximum of source and sink?
It's a function of both.
If your GPIO pad is sourcing current, then it's effectively connecting VDDIO via a resistor to the GPIO. Similarly, if the GPIO is sinking current, then it's connecting VSSIO via resistor to the GPIO.
There are a set number of VDDIO and VSSIO pads connected to each GPIO bank. The number and dispersion of these determines how much aggregate current you can source/sink at any one time, as you have several factors to consider.
As said previously, the current must go via the package ball(s), through the in-package substrate (basically a little high-density PCB that mounts the silicon die), through the teensy bond wires and on to the chip.
There are also semiconductor effects with sourcing/sinking large amounts of current - the metal layers on the chip that transmit the current from the power pads to the GPIOs contribute to series resistance and as such there will be a voltage gradient across the row of GPIO pads. Too much voltage gradient and things start to get reverse biased, leak, overheat locally etc.
I would say that the 50mA global limit applies to simultaneous source and sink currents.
I trust/believe in information that can be verified.
You have someone who was on the design team of the chip in question stating facts about the design. You have multiple posters in this thread with extensive academic and professional qualifications related to chip design providing their informed opinions. What sort of verification are you expecting, if not words from the horse's mouth?
Rockets are loud.