The SOC chip is a BGA type with over 300 connection points. https://en.wikipedia.org/wiki/Ball_grid_arrayRoboTrader wrote: ↑Sat Jan 06, 2018 1:29 pmHello in a great programming New Year!
I have two questions:
1: The more philosophical question:
Why the pins are in order like they are? Why they do not build it with 2 Pins on one side with 5V, 3.3V and GND, then all the programmable ones? Why this "chaos"? Is this because of the micro controller? Or why?
Not sure what you mean by "speculation"? The pinout has been pretty solid for a long time:RoboTrader wrote: ↑Sat Jan 06, 2018 1:29 pm2: The knowledge question:
I read many different versions of which pins are used for SPI, for I2C, ... For me it would be great to "see" all the assignment in configuration files or anything like that on my Pi instead of "speculations". Or can I measure it at the pins myself?
Or do you have the official assignment of the pins for all the Interfaces?
Thanks a lot and a great weekend
I'm sorry if it sounds like "I don't like it". I was just wandering for the (for me) chaos and interested in an explanation.It is very difficult to route the traces (tracks) even with a 6 layer board that the RPi has and using automatic routing software. So I think the RPF did as well as possible with the layout that we now have.
Two situations are real reasons for my doubts:Not sure what you mean by "speculation"? The pinout has been pretty solid for a long time:
The link is the same I used for my "pin graph".Here is a good reference: https://pinout.xyz/
You can also type pinout on the RPi at the command prompt.
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