Imobius
Posts: 2
Joined: Sun May 31, 2015 7:14 pm

3.5 Inch SSD2119 TFT Display and Notro's FBTFT

Sun May 31, 2015 7:26 pm

I am trying to get my 3.5 Inch TFT Display with the SSD2119 Controller to work using Notro's TFT Drivers on a Raspberry Pi Compute Module embedded in a custom board. From what I understand, the SSD2119 is almost identical to the SSD1289. I noticed that Notro's fbtft_device driver has a sainsmart32_spi module that supports the SSD1289. I tried the following commands ( while providing my reset and dc pins with my custom design ), and I get a /dev/fb1 device created. But when I 'sudo cat /dev/urandom > /dev/fb1', I see nothing on the screen. The Screen is powered and I can toggle the enable line with /sys/class/gpio to turn it on and off. What am I doing wrong? How can I get this to work?

>> sudo modprobe -r fbtft_device
>> sudo dmesg -C
>> sudo modprobe fbtft_device name=sainsmart32_spi rotate=90 speed=16000000 debug=$((1<<5)) gpios=reset:4,dc:9
>> dmesg
[ 3320.776805] fbtft_device: module is from the staging directory, the quality is unknown, you have been warned.
[ 3320.781972] fbtft_device: SPI devices registered:
[ 3320.782840] fbtft_device: spidev spi0.1 500kHz 8 bits mode=0x00
[ 3320.782870] fbtft_device: 'fb' Platform devices registered:
[ 3320.782923] fbtft_device: bcm2708_fb id=-1 pdata? no
[ 3321.055168] fb_ssd1289 spi0.0: Display update: 1239 kB/s (120.963 ms), fps=0 (0.000 ms)
[ 3321.064055] graphics fb1: fb_ssd1289 frame buffer, 320x240, 150 KiB video memory, 4 KiB DMA buffer memory, fps=20, spi0.0 at 16 MHz
[ 3321.064175] fbtft_device: GPIOS used by 'sainsmart32_spi':
[ 3321.064198] fbtft_device: 'reset' = GPIO4
[ 3321.064211] fbtft_device: 'dc' = GPIO9
[ 3321.064222] fbtft_device: SPI devices registered:
[ 3321.064241] fbtft_device: spidev spi0.1 500kHz 8 bits mode=0x00
[ 3321.064257] fbtft_device: fb_ssd1289 spi0.0 16000kHz 8 bits mode=0x00

Here are the components in the schematic relating to the Display:
Image
Image

notro
Posts: 686
Joined: Tue Oct 16, 2012 6:21 pm
Location: Drammen, Norway

Re: 3.5 Inch SSD2119 TFT Display and Notro's FBTFT

Sun May 31, 2015 9:03 pm

It could be that the default init sequence in fb_ssd1289 does not match your display.
An uninitialized display is white, so when the driver is loaded you should get a backlit black display.
You will always get /dev/fb1 even if there is no display connected, the driver doesn't check.
See if you can get some example code for the display, it will contain the init sequence.

init= parameter: https://github.com/notro/fbtft/wiki/fbt ... parameters

Imobius
Posts: 2
Joined: Sun May 31, 2015 7:14 pm

Re: 3.5 Inch SSD2119 TFT Display and Notro's FBTFT

Thu Jun 04, 2015 1:22 am

Wow - I found some example init code - copied into the init function in fb_ssd1289.c , rebuilt the driver and I can 'cat /dev/urandom > /dev/fb1'!

Thanks for the support Notro :)

Spelan
Posts: 4
Joined: Wed Nov 11, 2015 7:51 am

Re: 3.5 Inch SSD2119 TFT Display and Notro's FBTFT

Wed Nov 11, 2015 10:00 am

Hello Imobius,

Did you get SSD2119 completely working with raspberry?
Not just sudo cat /dev/urandom > /dev/fb1.

I got picture from sudo cat /dev/urandom > /dev/fb1, but I don't have a normal picture of FB.
I have a three copies that are shifted and the picture look through several pixels like a zebra.

Original picture is
http://art110.wikispaces.com/file/view/Mystery-100x100.jpg/30649064/Mystery-100x100.jpg

But my picture is below.

Thank you.
Attachments
IMAG1105.jpg
IMAG1105.jpg (34.55 KiB) Viewed 1932 times

Spelan
Posts: 4
Joined: Wed Nov 11, 2015 7:51 am

Re: 3.5 Inch SSD2119 TFT Display and Notro's FBTFT

Wed Nov 11, 2015 11:48 am

I have changed a file fb_ssd1289, I changed an initialisation.

My init code is below, I got this file from supplier website

// SSD2119 - START INIT
write_reg(par, 0x0028, 0x0006);
//write_command(0x0028); // VCOM OTP
//write_data(0x0006); // Page 55-56 of SSD2119 datasheet

write_reg(par, 0x0000, 0x0001);
//write_command(0x0000); // start Oscillator
//write_data(0x0001); // Page 36 of SSD2119 datasheet

write_reg(par, 0x0010, 0x0000);
//write_command(0x0010); // Sleep mode
//write_data(0x0000); // Page 49 of SSD2119 datasheet

write_reg(par, 0x0001, 0x32EF);
//write_command(0x0001); // Driver Output Control
//write_data(0x32EF); // Page 36-39 of SSD2119 datasheet

write_reg(par, 0x0002, 0x0600);
//write_command(0x0002); // LCD Driving Waveform Control
//write_data(0x0600); // Page 40-42 of SSD2119 datasheet

write_reg(par, 0x0003, 0x6A38);
//write_command(0x0003); // Power Control 1
//write_data(0x6A38); // Page 43-44 of SSD2119 datasheet

write_reg(par, 0x0011, 0x6870);
//write_command(0x0011); // Entry Mode
//write_data(0x6870); // Page 50-52 of SSD2119 datasheet

write_reg(par, 0x000F, 0x0000);
//write_command(0X000F); // Gate Scan Position
//write_data(0x0000); // Page 49 of SSD2119 datasheet

write_reg(par, 0X000B, 0x5308);
//write_command(0X000B); // Frame Cycle Control
//write_data(0x5308); // Page 45 of SSD2119 datasheet

write_reg(par, 0X000C, 0x0003);
//write_command(0x000C); // Power Control 2
//write_data(0x0003); // Page 47 of SSD2119 datasheet

write_reg(par, 0X000D, 0x000A);
//write_command(0x000D); // Power Control 3
//write_data(0x000A); // Page 48 of SSD2119 datasheet

write_reg(par, 0x000E, 0x2E00);
//write_command(0x000E); // Power Control 4
//write_data(0x2E00); // Page 48 of SSD2119 datasheet

write_reg(par, 0x001E, 0x00BE);
//write_command(0x001E); // Power Control 5
//write_data(0x00BE); // Page 53 of SSD2119 datasheet

write_reg(par, 0x0025, 0x8000);
//write_command(0x0025); // Frame Frequency Control
//write_data(0x8000); // Page 53 of SSD2119 datasheet

write_reg(par, 0x0026, 0x7800);
//write_command(0x0026); // Analog setting
//write_data(0x7800); // Page 54 of SSD2119 datasheet

write_reg(par, 0x004E, 0x0000);
//write_command(0x004E); // Ram Address Set
//write_data(0x0000); // Page 58 of SSD2119 datasheet

write_reg(par, 0x004F, 0x0000);
//write_command(0x004F); // Ram Address Set
//write_data(0x0000); // Page 58 of SSD2119 datasheet

write_reg(par, 0x0012, 0x08D9);
//write_command(0x0012); // Sleep mode
//write_data(0x08D9); // Page 49 of SSD2119 datasheet

// Gamma Control (R30h to R3Bh) -- Page 56 of SSD2119 datasheet
write_reg(par, 0x0030, 0x0000);
//write_command(0x0030);
//write_data(0x0000);

write_reg(par, 0x0031, 0x0104);
//write_command(0x0031);
//write_data(0x0104);

write_reg(par, 0x0032, 0x0100);
//write_command(0x0032);
//write_data(0x0100);

write_reg(par, 0x0033, 0x0305);
//write_command(0x0033);
//write_data(0x0305);

write_reg(par, 0x0034, 0x0505);
//write_command(0x0034);
//write_data(0x0505);

write_reg(par, 0x0035, 0x0305);
//write_command(0x0035);
//write_data(0x0305);

write_reg(par, 0x0036, 0x0707);
//write_command(0x0036);
//write_data(0x0707);

write_reg(par, 0x0037, 0x0300);
//write_command(0x0037);
//write_data(0x0300);

write_reg(par, 0x003A, 0x1200);
//write_command(0x003A);
//write_data(0x1200);

write_reg(par, 0x003B, 0x0800);
//write_command(0x003B);
//write_data(0x0800);

write_reg(par, 0x0007, 0x0033);
//write_command(0x0007); // Display Control
//write_data(0x0033); // Page 45 of SSD2119 datasheet

//delay(150);

write_reg(par, 0x0022);
//write_command(0x0022); // RAM data write/read
// SSD2119 - END

PhilBot
Posts: 15
Joined: Wed Nov 12, 2014 8:39 pm

Re: 3.5 Inch SSD2119 TFT Display and Notro's FBTFT

Sat Mar 18, 2017 11:57 pm

Hi Spelan,

I'm trying to get this driver to work again with the same display on a Compute Module 3. I have lost my original fb_ssd2119.c and so far cannot get the driver to work again.

I've pasted what I have below. Would you mind sharing the complete fb_ssd2119.c file you used to get it to work. I'd really appreciate it thanks!

Code: Select all

/*
 * FB driver for the SSD1289 LCD Controller
 *
 * Copyright (C) 2013 Noralf Tronnes
 *
 * Init sequence taken from ITDB02_Graph16.cpp - (C)2010-2011 Henning Karlsen
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/gpio.h>

#include "fbtft.h"

#define DRVNAME		"fb_ssd2119"
#define WIDTH		240
#define HEIGHT		320
#define DEFAULT_GAMMA	"02 03 2 5 7 7 4 2 4 2\n" \
			"02 03 2 5 7 5 4 2 4 2"

static unsigned int reg11 = 0x6040;
module_param(reg11, uint, 0);
MODULE_PARM_DESC(reg11, "Register 11h value");

static int init_display(struct fbtft_par *par)
{
	par->fbtftops.reset(par);

        printk(KERN_ERR "fb_ssd2119: Calling init()\n");

	if (par->gpio.cs != -1)
		gpio_set_value(par->gpio.cs, 0);  /* Activate chip */

// SSD2119 - START INIT
write_reg(par, 0x0028, 0x0006);
//write_command(0x0028); // VCOM OTP
//write_data(0x0006); // Page 55-56 of SSD2119 datasheet

write_reg(par, 0x0000, 0x0001);
//write_command(0x0000); // start Oscillator
//write_data(0x0001); // Page 36 of SSD2119 datasheet

write_reg(par, 0x0010, 0x0000);
//write_command(0x0010); // Sleep mode
//write_data(0x0000); // Page 49 of SSD2119 datasheet

write_reg(par, 0x0001, 0x32EF);
//write_command(0x0001); // Driver Output Control
//write_data(0x32EF); // Page 36-39 of SSD2119 datasheet

write_reg(par, 0x0002, 0x0600);
//write_command(0x0002); // LCD Driving Waveform Control
//write_data(0x0600); // Page 40-42 of SSD2119 datasheet

write_reg(par, 0x0003, 0x6A38);
//write_command(0x0003); // Power Control 1
//write_data(0x6A38); // Page 43-44 of SSD2119 datasheet

write_reg(par, 0x0011, 0x6870);
//write_command(0x0011); // Entry Mode
//write_data(0x6870); // Page 50-52 of SSD2119 datasheet

write_reg(par, 0x000F, 0x0000);
//write_command(0X000F); // Gate Scan Position
//write_data(0x0000); // Page 49 of SSD2119 datasheet

write_reg(par, 0X000B, 0x5308);
//write_command(0X000B); // Frame Cycle Control
//write_data(0x5308); // Page 45 of SSD2119 datasheet

write_reg(par, 0X000C, 0x0003);
//write_command(0x000C); // Power Control 2
//write_data(0x0003); // Page 47 of SSD2119 datasheet

write_reg(par, 0X000D, 0x000A);
//write_command(0x000D); // Power Control 3
//write_data(0x000A); // Page 48 of SSD2119 datasheet

write_reg(par, 0x000E, 0x2E00);
//write_command(0x000E); // Power Control 4
//write_data(0x2E00); // Page 48 of SSD2119 datasheet

write_reg(par, 0x001E, 0x00BE);
//write_command(0x001E); // Power Control 5
//write_data(0x00BE); // Page 53 of SSD2119 datasheet

write_reg(par, 0x0025, 0x8000);
//write_command(0x0025); // Frame Frequency Control
//write_data(0x8000); // Page 53 of SSD2119 datasheet

write_reg(par, 0x0026, 0x7800);
//write_command(0x0026); // Analog setting
//write_data(0x7800); // Page 54 of SSD2119 datasheet

write_reg(par, 0x004E, 0x0000);
//write_command(0x004E); // Ram Address Set
//write_data(0x0000); // Page 58 of SSD2119 datasheet

write_reg(par, 0x004F, 0x0000);
//write_command(0x004F); // Ram Address Set
//write_data(0x0000); // Page 58 of SSD2119 datasheet

write_reg(par, 0x0012, 0x08D9);
//write_command(0x0012); // Sleep mode
//write_data(0x08D9); // Page 49 of SSD2119 datasheet

// Gamma Control (R30h to R3Bh) -- Page 56 of SSD2119 datasheet
write_reg(par, 0x0030, 0x0000);
//write_command(0x0030);
//write_data(0x0000);

write_reg(par, 0x0031, 0x0104);
//write_command(0x0031);
//write_data(0x0104);

write_reg(par, 0x0032, 0x0100);
//write_command(0x0032);
//write_data(0x0100);

write_reg(par, 0x0033, 0x0305);
//write_command(0x0033);
//write_data(0x0305);

write_reg(par, 0x0034, 0x0505);
//write_command(0x0034);
//write_data(0x0505);

write_reg(par, 0x0035, 0x0305);
//write_command(0x0035);
//write_data(0x0305);

write_reg(par, 0x0036, 0x0707);
//write_command(0x0036);
//write_data(0x0707);

write_reg(par, 0x0037, 0x0300);
//write_command(0x0037);
//write_data(0x0300);

write_reg(par, 0x003A, 0x1200);
//write_command(0x003A);
//write_data(0x1200);

write_reg(par, 0x003B, 0x0800);
//write_command(0x003B);
//write_data(0x0800);	

write_reg(par, 0x0007, 0x0033);
//write_command(0x0007); // Display Control 
//write_data(0x0033); // Page 45 of SSD2119 datasheet

//delay(150);

write_reg(par, 0x0022);
//write_command(0x0022); // RAM data write/read
// SSD2119 - END

	return 0;
}

static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
{

        printk(KERN_ERR "fb_ssd2119: calling set_addr_win\n");
        return;

	switch (par->info->var.rotate) {
	/* R4Eh - Set GDDRAM X address counter */
	/* R4Fh - Set GDDRAM Y address counter */
	case 0:
		write_reg(par, 0x4e, xs);
		write_reg(par, 0x4f, ys);
		break;
	case 180:
		write_reg(par, 0x4e, par->info->var.xres - 1 - xs);
		write_reg(par, 0x4f, par->info->var.yres - 1 - ys);
		break;
	case 270:
		write_reg(par, 0x4e, par->info->var.yres - 1 - ys);
		write_reg(par, 0x4f, xs);
		break;
	case 90:
		write_reg(par, 0x4e, ys);
		write_reg(par, 0x4f, par->info->var.xres - 1 - xs);
		break;
	}

	/* R22h - RAM data write */
	write_reg(par, 0x22);
}

static int set_var(struct fbtft_par *par)
{
	if (par->fbtftops.init_display != init_display) {
		/* don't risk messing up register 11h */
		fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
			"%s: skipping since custom init_display() is used\n",
			__func__);
		return 0;
	}

        printk(KERN_ERR "fb_ssd2119: Calling set_var\n");

        return 0;

	switch (par->info->var.rotate) {
	case 0:
		write_reg(par, 0x11, reg11 | 0x30);
		break;
	case 270:
		write_reg(par, 0x11, reg11 | 0x28);
		break;
	case 180:
		write_reg(par, 0x11, reg11 | 0x00);
		break;
	case 90:
		write_reg(par, 0x11, reg11 | 0x18);
		break;
	}

	return 0;
}

/*
 * Gamma string format:
 * VRP0 VRP1 PRP0 PRP1 PKP0 PKP1 PKP2 PKP3 PKP4 PKP5
 * VRN0 VRN1 PRN0 PRN1 PKN0 PKN1 PKN2 PKN3 PKN4 PKN5
 */
#define CURVE(num, idx)  curves[num * par->gamma.num_values + idx]
static int set_gamma(struct fbtft_par *par, unsigned long *curves)
{

        printk(KERN_ERR "fb_ssd2119: Calling set_gamma\n");

        return 0;
	unsigned long mask[] = {
		0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
		0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
	};
	int i, j;

	/* apply mask */
	for (i = 0; i < 2; i++)
		for (j = 0; j < 10; j++)
			CURVE(i, j) &= mask[i * par->gamma.num_values + j];

	write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4));
	write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6));
	write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8));
	write_reg(par, 0x0033, CURVE(0, 3) << 8 | CURVE(0, 2));
	write_reg(par, 0x0034, CURVE(1, 5) << 8 | CURVE(1, 4));
	write_reg(par, 0x0035, CURVE(1, 7) << 8 | CURVE(1, 6));
	write_reg(par, 0x0036, CURVE(1, 9) << 8 | CURVE(1, 8));
	write_reg(par, 0x0037, CURVE(1, 3) << 8 | CURVE(1, 2));
	write_reg(par, 0x003A, CURVE(0, 1) << 8 | CURVE(0, 0));
	write_reg(par, 0x003B, CURVE(1, 1) << 8 | CURVE(1, 0));

	return 0;
}
#undef CURVE

static struct fbtft_display display = {
	.regwidth = 16,
	.width = WIDTH,
	.height = HEIGHT,
	.gamma_num = 2,
	.gamma_len = 10,
	.gamma = DEFAULT_GAMMA,
	.fbtftops = {
		.init_display = init_display,
		.set_addr_win = set_addr_win,
		.set_var = set_var,
		.set_gamma = set_gamma,
	},
};

FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd2119", &display);

MODULE_ALIAS("spi:" DRVNAME);
MODULE_ALIAS("platform:" DRVNAME);
MODULE_ALIAS("spi:ssd2119");
MODULE_ALIAS("platform:ssd2119");

MODULE_DESCRIPTION("FB driver for the SSD2119 LCD Controller");
MODULE_AUTHOR("Noralf Tronnes");
MODULE_LICENSE("GPL");

Spelan
Posts: 4
Joined: Wed Nov 11, 2015 7:51 am

Re: 3.5 Inch SSD2119 TFT Display and Notro's FBTFT

Sun Mar 19, 2017 9:20 pm

Hi PhilBot,
please have it.
I got this driver working!

/*
* FB driver for the SSD1289 LCD Controller
*
* Copyright (C) 2013 Noralf Tronnes
*
* Init sequence taken from ITDB02_Graph16.cpp - (C)2010-2011 Henning Karlsen
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/gpio.h>

#include "fbtft.h"

#define DRVNAME "fb_ssd1289"
#define WIDTH 320
#define HEIGHT 240
#define DEFAULT_GAMMA "02 03 2 5 7 7 4 2 4 2\n" \
"02 03 2 5 7 5 4 2 4 2"

// color definitions
#define BLACK 0x0000
#define BLUE 0x001F
#define RED 0xF800
#define GREEN 0x07E0
#define CYAN 0x07FF
#define MAGENTA 0xF81F
#define YELLOW 0xFFE0
#define WHITE 0xFFFF


static unsigned reg11 = 0x6040;
module_param(reg11, uint, 0);
MODULE_PARM_DESC(reg11, "Register 11h value");


static int init_display(struct fbtft_par *par)
{
fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);

par->fbtftops.reset(par);

if (par->gpio.cs != -1)
gpio_set_value(par->gpio.cs, 0); /* Activate chip */

//--------------------------------------------------------------------
// SSD2119 - START INIT
write_reg(par, 0x0028, 0x0006);
//write_command(0x0028); // VCOM OTP
//write_data(0x0006); // Page 55-56 of SSD2119 datasheet

write_reg(par, 0x0000, 0x0001);
//write_command(0x0000); // start Oscillator
//write_data(0x0001); // Page 36 of SSD2119 datasheet

write_reg(par, 0x0010, 0x0000);
//write_command(0x0010); // Sleep mode
//write_data(0x0000); // Page 49 of SSD2119 datasheet

write_reg(par, 0x0001, 0x30EF);//32EF
//write_command(0x0001); // Driver Output Control
//write_data(0x72EF); // Page 36-39 of SSD2119 datasheet

write_reg(par, 0x0002, 0x0600);
//write_command(0x0002); // LCD Driving Waveform Control
//write_data(0x0600); // Page 40-42 of SSD2119 datasheet

write_reg(par, 0x0003, 0x6A38);
//write_command(0x0003); // Power Control 1
//write_data(0x6A38); // Page 43-44 of SSD2119 datasheet

write_reg(par, 0x0011, 0x6870);
//write_command(0x0011); // Entry Mode
//write_data(0x6870); // Page 50-52 of SSD2119 datasheet

write_reg(par, 0x000F, 0x0000);
//write_command(0X000F); // Gate Scan Position
//write_data(0x0000); // Page 49 of SSD2119 datasheet

write_reg(par, 0X000B, 0x5308);
//write_command(0X000B); // Frame Cycle Control
//write_data(0x5308); // Page 45 of SSD2119 datasheet

write_reg(par, 0X000C, 0x0003);
//write_command(0x000C); // Power Control 2
//write_data(0x0003); // Page 47 of SSD2119 datasheet

write_reg(par, 0X000D, 0x000A);
//write_command(0x000D); // Power Control 3
//write_data(0x000A); // Page 48 of SSD2119 datasheet

write_reg(par, 0x000E, 0x2E00);
//write_command(0x000E); // Power Control 4
//write_data(0x2E00); // Page 48 of SSD2119 datasheet

write_reg(par, 0x001E, 0x00BE);
//write_command(0x001E); // Power Control 5
//write_data(0x00BE); // Page 53 of SSD2119 datasheet

write_reg(par, 0x0025, 0x8000);
//write_command(0x0025); // Frame Frequency Control
//write_data(0x8000); // Page 53 of SSD2119 datasheet

write_reg(par, 0x0026, 0x7800);
//write_command(0x0026); // Analog setting
//write_data(0x7800); // Page 54 of SSD2119 datasheet

write_reg(par, 0x004E, 0x0000);
//write_command(0x004E); // Ram Address Set
//write_data(0x0000); // Page 58 of SSD2119 datasheet

write_reg(par, 0x004F, 0x0000);
//write_command(0x004F); // Ram Address Set
//write_data(0x0000); // Page 58 of SSD2119 datasheet

write_reg(par, 0x0012, 0x08D9);
//write_command(0x0012); // Sleep mode
//write_data(0x08D9); // Page 49 of SSD2119 datasheet

// Gamma Control (R30h to R3Bh) -- Page 56 of SSD2119 datasheet
write_reg(par, 0x0030, 0x0000);
//write_command(0x0030);
//write_data(0x0000);

write_reg(par, 0x0031, 0x0104);
//write_command(0x0031);
//write_data(0x0104);

write_reg(par, 0x0032, 0x0100);
//write_command(0x0032);
//write_data(0x0100);

write_reg(par, 0x0033, 0x0305);
//write_command(0x0033);
//write_data(0x0305);

write_reg(par, 0x0034, 0x0505);
//write_command(0x0034);
//write_data(0x0505);

write_reg(par, 0x0035, 0x0305);
//write_command(0x0035);
//write_data(0x0305);

write_reg(par, 0x0036, 0x0707);
//write_command(0x0036);
//write_data(0x0707);

write_reg(par, 0x0037, 0x0300);
//write_command(0x0037);
//write_data(0x0300);

write_reg(par, 0x003A, 0x1200);
//write_command(0x003A);
//write_data(0x1200);

write_reg(par, 0x003B, 0x0800);
//write_command(0x003B);
//write_data(0x0800);

write_reg(par, 0x0007, 0x0033);
//write_command(0x0007); // Display Control
//write_data(0x0033); // Page 45 of SSD2119 datasheet

//delay(150);

//------------------------------------------------------------
write_reg(par, 0x0044, 0xEF00);
//write_command(0x0044); // Vertical RAM address position
//write_data(0xEF00); // Page 57 of SSD2119 datasheet
write_reg(par, 0x0045, 0x0000);
//write_command(0x0045); // Horizontal RAM address position
//write_data(0x0000); // Page 57 of SSD2119 datasheet
write_reg(par, 0x0046, 0x013F);
//write_command(0x0046); // Horizontal RAM address position
//write_data(0x013F); // Page 57 of SSD2119 datasheet
//------------------------------------------------------------



write_reg(par, 0x0022);
//write_command(0x0022); // RAM data write/read
// SSD2119 - END
//-------------------------------------------------------------------------
/*
write_reg(par, 0x00, 0x0001);
write_reg(par, 0x03, 0xA8A4);
write_reg(par, 0x0C, 0x0000);
write_reg(par, 0x0D, 0x080C);
write_reg(par, 0x0E, 0x2B00);
write_reg(par, 0x1E, 0x00B7);
write_reg(par, 0x01,
(1 << 13) | (par->bgr << 11) | (1 << 9) | (HEIGHT - 1));
write_reg(par, 0x02, 0x0600);
write_reg(par, 0x10, 0x0000);
write_reg(par, 0x05, 0x0000);
write_reg(par, 0x06, 0x0000);
write_reg(par, 0x16, 0xEF1C);
write_reg(par, 0x17, 0x0003);
write_reg(par, 0x07, 0x0233);
write_reg(par, 0x0B, 0x0000);
write_reg(par, 0x0F, 0x0000);
write_reg(par, 0x41, 0x0000);
write_reg(par, 0x42, 0x0000);
write_reg(par, 0x48, 0x0000);
write_reg(par, 0x49, 0x013F);
write_reg(par, 0x4A, 0x0000);
write_reg(par, 0x4B, 0x0000);
write_reg(par, 0x44, 0xEF00);
write_reg(par, 0x45, 0x0000);
write_reg(par, 0x46, 0x013F);
write_reg(par, 0x23, 0x0000);
write_reg(par, 0x24, 0x0000);
write_reg(par, 0x25, 0x8000);
write_reg(par, 0x4f, 0x0000);
write_reg(par, 0x4e, 0x0000);
write_reg(par, 0x22);
*/
return 0;
}

static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
{
fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
"%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);

switch (par->info->var.rotate) {
/* R4Eh - Set GDDRAM X address counter */
/* R4Fh - Set GDDRAM Y address counter */
case 0:
write_reg(par, 0x4e, xs);
write_reg(par, 0x4f, ys);
break;
case 180:
write_reg(par, 0x4e, par->info->var.xres - 1 - xs);
write_reg(par, 0x4f, par->info->var.yres - 1 - ys);
break;
case 270:
write_reg(par, 0x4e, par->info->var.yres - 1 - ys);
write_reg(par, 0x4f, xs);
break;
case 90:
write_reg(par, 0x4e, ys);
write_reg(par, 0x4f, par->info->var.xres - 1 - xs);
break;
}

/* R22h - RAM data write */
write_reg(par, 0x22);
}

static int set_var(struct fbtft_par *par)
{
unsigned int aa,bb;// temp

fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);

if (par->fbtftops.init_display != init_display) {
/* don't risk messing up register 11h */
fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
"%s: skipping since custom init_display() is used\n",
__func__);
return 0;
}

switch (par->info->var.rotate) {
case 0:
write_reg(par, 0x11, reg11 | 0b110000);
break;
case 270:
write_reg(par, 0x11, reg11 | 0b101000);
break;
case 180:
write_reg(par, 0x11, reg11 | 0b000000);
break;
case 90:
write_reg(par, 0x11, reg11 | 0b011000);
break;
}

/*
for(aa=0;aa<320;aa++)
{
for(bb=0;bb<240;bb++)
{
if(aa>279)write_reg(par,BLACK);
else if(aa>239)write_reg(par,BLUE);
else if(aa>199)write_reg(par,GREEN);
else if(aa>159)write_reg(par,CYAN);
else if(aa>119)write_reg(par,RED);
else if(aa>79)write_reg(par,MAGENTA);
else if(aa>39)write_reg(par,YELLOW);
else write_reg(par,WHITE);
}
}
*/
return 0;
}

/*
Gamma string format:
VRP0 VRP1 PRP0 PRP1 PKP0 PKP1 PKP2 PKP3 PKP4 PKP5
VRN0 VRN1 PRN0 PRN1 PKN0 PKN1 PKN2 PKN3 PKN4 PKN5
*/
#define CURVE(num, idx) curves[num*par->gamma.num_values + idx]
static int set_gamma(struct fbtft_par *par, unsigned long *curves)
{
unsigned long mask[] = {
0b11111, 0b11111, 0b111, 0b111, 0b111,
0b111, 0b111, 0b111, 0b111, 0b111,
0b11111, 0b11111, 0b111, 0b111, 0b111,
0b111, 0b111, 0b111, 0b111, 0b111 };
int i, j;

fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);

/* apply mask */
for (i = 0; i < 2; i++)
for (j = 0; j < 10; j++)
CURVE(i, j) &= mask[i*par->gamma.num_values + j];

write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4));
write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6));
write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8));
write_reg(par, 0x0033, CURVE(0, 3) << 8 | CURVE(0, 2));
write_reg(par, 0x0034, CURVE(1, 5) << 8 | CURVE(1, 4));
write_reg(par, 0x0035, CURVE(1, 7) << 8 | CURVE(1, 6));
write_reg(par, 0x0036, CURVE(1, 9) << 8 | CURVE(1, 8));
write_reg(par, 0x0037, CURVE(1, 3) << 8 | CURVE(1, 2));
write_reg(par, 0x003A, CURVE(0, 1) << 8 | CURVE(0, 0));
write_reg(par, 0x003B, CURVE(1, 1) << 8 | CURVE(1, 0));

return 0;
}
#undef CURVE


static struct fbtft_display display = {
.regwidth = 16,
.width = WIDTH,
.height = HEIGHT,
.gamma_num = 2,
.gamma_len = 10,
.gamma = DEFAULT_GAMMA,
.fbtftops = {
.init_display = init_display,
.set_addr_win = set_addr_win,
.set_var = set_var,
.set_gamma = set_gamma,
},
};
FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1289", &display);

MODULE_ALIAS("spi:" DRVNAME);
MODULE_ALIAS("platform:" DRVNAME);
MODULE_ALIAS("spi:ssd1289");
MODULE_ALIAS("platform:ssd1289");

MODULE_DESCRIPTION("FB driver for the SSD1289 LCD Controller");
MODULE_AUTHOR("Noralf Tronnes");
MODULE_LICENSE("GPL");
Attachments
IMAG1126_small.jpg
IMAG1126_small.jpg (59.54 KiB) Viewed 1128 times

PhilBot
Posts: 15
Joined: Wed Nov 12, 2014 8:39 pm

Re: 3.5 Inch SSD2119 TFT Display and Notro's FBTFT

Tue Mar 21, 2017 1:47 am

Thanks for the file. I've tried it but unfortunately, I see a white screen only. Nothing is actually written to /dev/fb1.

From what I've seen on Notro's wiki is that the white screen means the LCD is not initialized properly. If you have any ideas I would be very grateful to hear them. Thanks!

Here are the dmesg messages:

Code: Select all

[   59.212112] fbtft: module is from the staging directory, the quality is unknown, you have been warned.
[   59.222904] fbtft_device: module is from the staging directory, the quality is unknown, you have been warned.
[   59.223606] spidev spi0.0: spidev spi0.0 500kHz 8 bits mode=0x00
[   59.223613] spidev spi0.1: spidev spi0.1 500kHz 8 bits mode=0x00
[   59.223636] bcm2708_fb soc:fb: soc:fb id=-1 pdata? no
[   59.223662] spidev spi0.0: Deleting spi0.0
[   59.224089] fbtft_device: GPIOS used by 'sainsmart32_spi':
[   59.224092] fbtft_device: 'reset' = GPIO4
[   59.224094] fbtft_device: 'dc' = GPIO9
[   59.224100] spidev spi0.1: spidev spi0.1 500kHz 8 bits mode=0x00
[   59.224106] spi spi0.0: fb_ssd2119 spi0.0 16000kHz 8 bits mode=0x00
[ 1201.439124] fb_ssd2119: module is from the staging directory, the quality is unknown, you have been warned.
[ 1201.439691] fb_ssd2119 spi0.0: fbtft_gamma_parse_str() str=
[ 1201.439697] fb_ssd2119 spi0.0: 02 03 2 5 7 7 4 2 4 2
02 03 2 5 7 5 4 2 4 2
[ 1201.439721] fb_ssd2119 spi0.0: fbtft_request_gpios_match('reset')
[ 1201.439740] fb_ssd2119 spi0.0: fbtft_request_gpios: 'reset' = GPIO4
[ 1201.439744] fb_ssd2119 spi0.0: fbtft_request_gpios_match('dc')
[ 1201.439754] fb_ssd2119 spi0.0: fbtft_request_gpios: 'dc' = GPIO9
[ 1201.439758] fb_ssd2119 spi0.0: fbtft_verify_gpios()
[ 1201.439762] fb_ssd2119 spi0.0: init_display()
[ 1201.439766] fb_ssd2119 spi0.0: fbtft_reset()
[ 1201.559854] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0028 0006
[ 1201.559862] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 28
[ 1201.559892] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 06
[ 1201.559916] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0000 0001
[ 1201.559921] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 00
[ 1201.559933] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 01
[ 1201.559946] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0010 0000
[ 1201.559950] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 10
[ 1201.559962] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 00
[ 1201.559974] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0001 30ef
[ 1201.559978] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 01
[ 1201.559990] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 30 ef
[ 1201.560003] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0002 0600
[ 1201.560007] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 02
[ 1201.560019] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 06 00
[ 1201.560031] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0003 6a38
[ 1201.560036] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 03
[ 1201.560047] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 6a 38
[ 1201.560059] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0011 6870
[ 1201.560064] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 11
[ 1201.560075] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 68 70
[ 1201.560087] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 000f 0000
[ 1201.560092] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 0f
[ 1201.560103] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 00
[ 1201.560115] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 000b 5308
[ 1201.560120] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 0b
[ 1201.560132] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 53 08
[ 1201.560143] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 000c 0003
[ 1201.560148] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 0c
[ 1201.560159] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 03
[ 1201.560171] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 000d 000a
[ 1201.560176] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 0d
[ 1201.560187] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 0a
[ 1201.560199] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 000e 2e00
[ 1201.560204] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 0e
[ 1201.560216] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 2e 00
[ 1201.560228] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 001e 00be
[ 1201.560232] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 1e
[ 1201.560244] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 be
[ 1201.560256] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0025 8000
[ 1201.560261] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 25
[ 1201.560272] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 80 00
[ 1201.560284] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0026 7800
[ 1201.560289] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 26
[ 1201.560300] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 78 00
[ 1201.560312] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 004e 0000
[ 1201.560317] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 4e
[ 1201.560328] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 00
[ 1201.560340] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 004f 0000
[ 1201.560345] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 4f
[ 1201.560356] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 00
[ 1201.560368] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0012 08d9
[ 1201.560372] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 12
[ 1201.560384] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 08 d9
[ 1201.560396] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0030 0000
[ 1201.560401] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 30
[ 1201.560412] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 00
[ 1201.560424] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0031 0104
[ 1201.560429] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 31
[ 1201.560440] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 01 04
[ 1201.560452] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0032 0100
[ 1201.560457] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 32
[ 1201.560468] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 01 00
[ 1201.560480] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0033 0305
[ 1201.560485] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 33
[ 1201.560496] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 03 05
[ 1201.560508] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0034 0505
[ 1201.560513] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 34
[ 1201.560525] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 05 05
[ 1201.560536] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0035 0305
[ 1201.560541] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 35
[ 1201.560553] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 03 05
[ 1201.560564] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0036 0707
[ 1201.560569] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 36
[ 1201.560581] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 07 07
[ 1201.560592] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0037 0300
[ 1201.560597] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 37
[ 1201.560608] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 03 00
[ 1201.560620] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 003a 1200
[ 1201.560625] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 3a
[ 1201.560637] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 12 00
[ 1201.560649] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 003b 0800
[ 1201.560654] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 3b
[ 1201.560666] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 08 00
[ 1201.560677] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0007 0033
[ 1201.560682] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 07
[ 1201.560693] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 33
[ 1201.560705] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0044 ef00
[ 1201.560710] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 44
[ 1201.560721] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): ef 00
[ 1201.560733] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0045 0000
[ 1201.560738] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 45
[ 1201.560749] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 00
[ 1201.560761] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0046 013f
[ 1201.560766] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 46
[ 1201.560778] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 01 3f
[ 1201.560789] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0022
[ 1201.560794] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 22
[ 1201.560805] fb_ssd2119 spi0.0: set_var()
[ 1201.560810] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0011 6058
[ 1201.560815] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 11
[ 1201.560826] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 60 58
[ 1201.560839] fb_ssd2119 spi0.0: fbtft_update_display(start_line=0, end_line=319)
[ 1201.560844] fb_ssd2119 spi0.0: set_addr_win(xs=0, ys=0, xe=239, ye=319)
[ 1201.560849] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 004e 0000
[ 1201.560854] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 4e
[ 1201.560866] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 00
[ 1201.560878] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 004f 00ef
[ 1201.560883] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 4f
[ 1201.560894] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 ef
[ 1201.560905] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0022
[ 1201.560910] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 22
[ 1201.560922] fb_ssd2119 spi0.0: fbtft_write_vmem16_bus8(offset=0, len=153600)
[ 1201.560990] fb_ssd2119 spi0.0: fbtft_write_spi(len=32768): 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...
[ 1201.571874] fb_ssd2119 spi0.0: fbtft_write_spi(len=32768): 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...
[ 1201.582515] fb_ssd2119 spi0.0: fbtft_write_spi(len=32768): 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...
[ 1201.593135] fb_ssd2119 spi0.0: fbtft_write_spi(len=32768): 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...
[ 1201.603735] fb_ssd2119 spi0.0: fbtft_write_spi(len=22528): 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...
[ 1201.611009] fb_ssd2119 spi0.0: Display update: 2990 kB/s, fps=0
[ 1201.611015] fb_ssd2119 spi0.0: set_gamma()
[ 1201.611023] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0030 0707
[ 1201.611029] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 30
[ 1201.611044] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 07 07
[ 1201.611056] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0031 0204
[ 1201.611061] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 31
[ 1201.611073] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 02 04
[ 1201.611085] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0032 0204
[ 1201.611090] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 32
[ 1201.611101] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 02 04
[ 1201.611113] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0033 0502
[ 1201.611118] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 33
[ 1201.611130] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 05 02
[ 1201.611142] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0034 0507
[ 1201.611146] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 34
[ 1201.611158] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 05 07
[ 1201.611170] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0035 0204
[ 1201.611175] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 35
[ 1201.611186] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 02 04
[ 1201.611198] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0036 0204
[ 1201.611203] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 36
[ 1201.611214] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 02 04
[ 1201.611226] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 0037 0502
[ 1201.611231] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 37
[ 1201.611242] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 05 02
[ 1201.611254] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 003a 0302
[ 1201.611259] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 3a
[ 1201.611271] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 03 02
[ 1201.611282] fb_ssd2119 spi0.0: fbtft_write_reg16_bus8: 003b 0302
[ 1201.611287] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 00 3b
[ 1201.611298] fb_ssd2119 spi0.0: fbtft_write_spi(len=2): 03 02
[ 1201.611310] fb_ssd2119 spi0.0: fbtft_register_backlight(): led pin not set, exiting.
[ 1201.611542] graphics fb1: fb_ssd2119 frame buffer, 240x320, 150 KiB video memory, 32 KiB DMA buffer memory, fps=20, spi0.0 at 16 MHz

Spelan
Posts: 4
Joined: Wed Nov 11, 2015 7:51 am

Re: 3.5 Inch SSD2119 TFT Display and Notro's FBTFT

Tue Mar 21, 2017 5:37 am

What is about your jumpers on the board display to select interface? Are they proper selected? Have you measure your spi with osciloscope or logic analyser?

PhilBot
Posts: 15
Joined: Wed Nov 12, 2014 8:39 pm

Re: 3.5 Inch SSD2119 TFT Display and Notro's FBTFT

Tue Mar 21, 2017 10:45 pm

I got it to work with your code ! Thanks - I had to load the fb_ssd2119 module *after* the fbtft_device module.

Oshel
Posts: 2
Joined: Sun May 21, 2017 8:26 pm

Re: 3.5 Inch SSD2119 TFT Display and Notro's FBTFT

Sun May 21, 2017 8:32 pm

Hello,

I'm sorry for (maybe) stupid question but I am looking for a directory of this .c file... I can't find it. Could you tell me where it is and how to rebuild the driver?

Btw, why don't you just use following commands with flexfb since it drives ssd1289 well?

Code: Select all

modprobe fbtft_device name=flexfb speed=16000000 gpios=reset:25,dc:24

modprobe flexfb debug=3 width=240 height=320 rotate=0 regwidth=16 setaddrwin=2 init=-1,0x0028,0x0006,-1,0x0000,0x0001,-1,0x0010,0x0000,-1,0x0001,0x32EF,-1,0x0002,0x0600,-1,0x0003,0x6A38,-1,0x0011,0x6870,-1,0x000F,0x0000,-1,0x000B,0x5308,-1,0x000C,0x0003,-1,0x000D,0x000A,-1,0x000E,0x2E00,-1,0x001E,0x00BE,-1,0x0025,0x8000,-1,0x0026,0x7800,-1,0x004E,0x0000,-1,0x004F,0x0000,-1,0x0012,0x08D9,-1,0x0030,0x0000,-1,0x0031,0x0104,-1,0x0032,0x0100,-1,0x0033,0x0305,-1,0x0034,0x0505,-1,0x0035,0x0305,-1,0x0036,0x0707,-1,0x0037,0x0300,-1,0x003A,0x1200,-1,0x003B,0x0800,-1,0x0007,0x0033,-2,150,-1,0x0000,0x0022,-3
Initialization is taken from few posts before from this thread. And the proof it works with ssd1289 is last post of this thread:

https://github.com/notro/fbtft/issues/72

Oshel
Posts: 2
Joined: Sun May 21, 2017 8:26 pm

Re: 3.5 Inch SSD2119 TFT Display and Notro's FBTFT

Tue May 23, 2017 6:38 pm

Hey!

I managed to run the display using flexfb with following initialization:

Code: Select all

modprobe fbtft_device name=flexfb speed=25000000 gpios=reset:25,dc:24 debug=3
modprobe flexfb width=320 height=240 regwidth=16 setaddrwin=2 rotate=180 init=-1,0x0000,0x0001,-1,0x0028,0x0006,-1,0x0027,0x006D,-1,0x0025,0xF000,-1,0x0010,0x0000,-1,0x0007,0x0033,-1,0x0011,0x6240,-1,0x0002,0x0600,-1,0x0003,0x040E,-1,0x0001,0x72EF,-1,0x000F,0x0000,-1,0x000B,0x5308,-1,0x000C,0x0007,-1,0x000D,0x0006,-1,0x000E,0x2D00,-1,0x001E,0x01DD,-1,0x0044,0xEF00,-1,0x0045,0x0000,-1,0x0046,0x013F,-1,0x0030,0x0102,-1,0x0031,0x0206,-1,0x0032,0x0100,-1,0x0033,0x0003,-1,0x0034,0x0706,-1,0x0035,0x0105,-1,0x0036,0x0506,-1,0x0037,0x0300,-1,0x003A,0x0000,-1,0x003B,0x0000,-3
The initialization is taken from AM-320240LGTMQW-00H display which I do own. The only adjustment I had to make was to change 262k colors to 65k (already included in the init above).

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