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Why no 4-lane CSI on the Zero?

Tue Apr 16, 2019 12:33 pm

The Raspberry Pi Zero CSI connector has the same pinout as the compute module IO board CSI connectors, but two of the four CSI data lanes are not connected. I always assumed it was because the BCM2835 didn't have a 4-lane CSI input. But I just realized the compute module v1.1 does have a 4-lane CSI input, connected to its venerable BCM2835.

So I'm wondering, why not route the zero CSI connector to the SoC's 4-lane CSI input? Is it because that specific variant of the BCM2835 doesn't expose these pins? Is it because the PCB layout is already too densely packed to accommodate another 5cm of differential pairs? Is it to simplify firmware/software portability across the (non-CM) Raspberry Pi product line? Is it to prevent the zero from cannibalizing the compute module market?

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Re: Why no 4-lane CSI on the Zero?

Tue Apr 16, 2019 12:42 pm

While I don't know for sure I strongly suspect it was PCB routing difficulties. The CM has extra layers (8 rather than 6 iirc) to allow them to bring out every pin on the chip.

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Re: Why no 4-lane CSI on the Zero?

Tue Apr 16, 2019 12:57 pm

Purely down to pcb routing. The Zero is already a pretty busy board before trying to get those 4 extra traces through.
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