Guzunty Pi. New users start here.

[guzunty]

Guzunty Pi is an add on board for the Raspberry Pi that has gathered quite a large number of users this year. It has also had some exposure in the MagPi magazine this month.

Accordingly, I wondered if it might not be a good time to create a topic dedicated to help new Guzunty adopters get up and running. I have not had a great many reports of difficulty with the programming software or the use of the hardware definition files (cores) available on GitHub. I've had even fewer (read, no) reports of failed builds or other problems getting the Guzunty hardware working.

Nevertheless, it seems like it would be good to have a place to discuss the use and capabilities of the Guzunty, so here it is. Please feel free to ask any questions you may have.

[texy]

Hi Guzunty,
as you know I recently purchase a Guzunty kit - very impressive.
Being very new to CPLD's I have a lot to learn. I think it would be useful if you could supply a tutorial explaining how to use VHD listings, from installing Xilinx ISE to programming the Guzunty with the generated .xsvf file, which is of course the correct format for the pi to program the CPLD.

Also one of the features of using the Guzunty board is the possibility of having additional GPIO lines - something that can be very useful for Pi users. I would like to see some python examples of using those additional I/O lines. The same could be applied for other languages as well of course, but python would be be preference.
Thanks,
Texy

[guzunty]

Hi Texy, thank you for a great couple of questions to get started with.

On the first question, yes. I really need to put together a page telling you where to get the development tool from. I will make this a priority and post back here when it is done.

On the second question, most of the examples are in C because that is the language I have most experience of. However, I did not neglect Python fans completely. You will find example Python programs for the gz_16i8o, gz_16o8i and gz_test cores. Look for a py file under each of the respective folders under the root src folder. There is also a setup.py program, together with supporting .c files under gz_lib. These create and export a python binding for Guzunty.

I hope that helps. I'll add something to the wiki to make the Python resources easier to find in the future.

[DaveTheWalker]

Hello Guzunty,

I also bought one of these kits recently, and had great fun soldering it together. My question is whether you could provide files and instructions for installing the Guzunty without a live internet connection?

My pi suffers behind a fairly substantial firewall, but I can get to it with a USB stick full of files.

Would this be at all possible?

Many thanks,
Dave

[guzunty]

Hi Dave,

Glad you enjoyed the build process.

There is a button on the lower right side of the GitHub web interface here:

https://github.com/Guzunty/Pi

The button is labelled 'Download Zip'. Click that and you'll have a copy of what you need that can go on a thumb drive.

Does that work for you?

[DaveTheWalker]

That's fantastic, I have all the files on there now, thanks.

Now all I need to do is find the page on the Wiki that tells me how to upload a core to the guzunty... I'm sure I found it once before(!)

UPDATE - I found it at the bottom of the build guide
Another UPDATE - I had to go and CHMOD the gz_load file, because it said I didn't have permission to run it. sudo didn't help... might just be me(!)

Dave

[DaveTheWalker]

Oh, and one more question while I'm at it... could you possibly knock up a version of gz_test that doesn't use FB3MC14 and FB3MC15, so that I can connect JP32 and JP34 and still have access to the Tx/Rx serial console?

I usually use the Pi headless, and SSH into it via a serial console (quirky, I know!) but it does require access to those two pins...

Cheers!
Dave

[guzunty]

> I had to go and CHMOD the gz_load file

You're right! I have updated the Set up your Pi page to include the chmod command.

> could you possibly knock up a version of gz_test that doesn't use FB3MC14 and FB3MC15

That would be quite easy, but I'm not clear on the requirement. I don't understand why you would want to be using GPIO14 and 15 while running the test core? Also, I'm not sure why you want to make JP32 and JP34. Those will route the Rx and Tx signals to the Guzunty.

If it was me and I wanted to keep using Tx and Rx to talk to my Pi, I'd build a Guzunty in the flexible configuration. That is, with a long pinned 2x13 header. Then I'd just connect the serial link through the extended pins as normal. Am I misunderstanding something?

Please, let me know how you want it to work.

[DaveTheWalker]

OK, I was right about the CHMOD, but wrong about the jumpers etc..

50% isn't too bad!

Good point about the Rx/Tx pins - I'd got confused with which way things were connected. I've already soldered on the socket to J1 now, so the flexible option is no longer an option, but I can certainly solder a couple of wires on instead.

UPDATE: - I've soldered on a 3-pin header for GND, Rx, Tx and it works perfectly. Very tidy and very functional.

Thanks for your tips!

By the way, I got it working with the test program yesterday, so I'm happy - I can't believe I have such a configurable CPLD on my Pi for such a low price. Next stop, VHDL! It's been a couple of years since I did any of that, but I'm sure it'll all come flooding back to me...

Thanks again,
Dave

[DaveTheWalker]

Hi again,

I was just playing with some of the other cores, and tried to "make" a couple. I get an error related to ncurses.h

pi@raspberrypi:~/Dave/guzunty/Pi-master/src/gz_8p8i$ make
make: Warning: File `Makefile' has modification time 4e+06 s in the future
gcc -g -O0 -Wall -I/usr/local/include -Winline -pipe -fPIC -DDEBUG_MODE gz_8p8i.c -o gz_8p8i -lgz -lbcm2835 -lrt -lncurses
gz_8p8i.c:27:21: fatal error: ncurses.h: No such file or directory
compilation terminated.
make: *** [all] Error 1

Am I supposed to already have ncurses.h on my system? If not, where can I get it from?

Thanks again,
Dave

[guzunty]

This should do the trick,

Code: Select all

sudo apt-get install ncurses

Unfortunately, if your pi is behind a firewall, I don't think this will work.

An alternative is to modify the C source to remove the dependencies on curses in the example code. For most cores, it is not absolutely essential. It is there to make the display pretty and to make it simpler to run the tests.

Please let me know how you get on with this.

It also looks like you have another issue with the pseudo real time clock on the Pi. This is probably also because you are behind a firewall. I ran into this at one point with an experimental kernel which did not have NTP enabled. I strongly recommend you find a fix for it if you are going to be building executables on your Pi.

The reason is that 'make' is strongly dependent on having good timestamps on files. The Pi has no hardware clock and relies on the NTP service to keep its pseudo clock lined up with reality. Without NTP, the Pi is forced to reload a cached value of time from when it was last shut down. This can put your file timestamps all over the place, with the symptom that 'make' becomes unreliable. It will not always rebuild everything that needs rebuilt when you issue the 'make' command.

You should be able to open a port for NTP in the firewall if you have access to it.

[DaveTheWalker]

Thanks for that - I think I'll have to take it home one weekend and plug it into a "live" network

Most of the time, I don't connect it to the network at all, and I'm frequently switching it off so the RTC gets reset every time. I hadn't realised this could cause trouble with "make", but it makes sense now you've mentioned it.

Maybe I'll add a little battery-backed RTC when I get a chance. It seems like a useful thing to have, anyway.

UPDATE: I just ordered a little DS1307 module from Amazon, so I'll modify that for the 3.3V I2C lines and wire that in when it arrives.

Thanks again,
Dave

p.s.... is it called "Guzunty" because it "Goes onto your" Pi?

[DaveTheWalker]

I've just been "playing" with Xilinx ISE, and I thought I'd made a nice inverter. I assigned the input to pin1 (FB1_pin2) and the output to pin 2 (FB1_pin5), and generated an xsvf file.

I programmed the file successfully onto the Guzunty, but once there, it doesn't do anything.

Whatever I make the input, the output is always low.

Any ideas what's gone wrong?

Thanks,
Dave

Code: Select all

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:07:40 07/03/2013 
-- Design Name: 
-- Module Name:    invert_top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity invert_top is
    Port ( PB : in  STD_LOGIC;
           LED : out  STD_LOGIC);
end invert_top;

architecture Behavioral of invert_top is

begin

	LED <= not PB;

end Behavioral;

[guzunty]

Hi Dave,

Your VHDL looks fine. Please post your constraints file (if you made one) and the fitter report.

The constraints file has a .ucf extension and the fitter report is the file with the .rpt extension.

Derek

[DaveTheWalker]

Code: Select all

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "LED"  LOC = "P2"  ;
NET "PB"  LOC = "P1"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

Code: Select all

cpldfit:  version P.40xd                            Xilinx Inc.
                                  Fitter Report
Design Name: invert_top                          Date:  7-11-2013,  3:29PM
Device Used: XC9572-7-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
1  /72  (  1%) 1   /360  (  1%) 1  /144 (  1%)   0  /72  (  0%) 2  /34  (  6%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1           1/18        1/36        1           1/90       1/ 9
FB2           0/18        0/36        0           0/90       0/ 9
FB3           0/18        0/36        0           0/90       0/ 8
FB4           0/18        0/36        0           0/90       0/ 8
             -----       -----                   -----       -----     
              1/72        1/144                   1/360      1/34 

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    1           1    |  I/O              :     2      28
Output        :    1           1    |  GCK/IO           :     0       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total      2           2

** Power Data **

There are 1 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'invert_top.ise'.
*************************  Summary of Mapped Logic  ************************

** 1 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
LED                 1     1     FB1_5   2    I/O     O       STD  FAST 

** 1 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
PB                  FB1_2   1    I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               1/35
Number of signals used by logic mapping into function block:  1
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
(unused)              0       0     0   5     FB1_2   1     I/O     I
(unused)              0       0     0   5     FB1_3         (b)     
(unused)              0       0     0   5     FB1_4         (b)     
LED                   1       0     0   4     FB1_5   2     I/O     O
(unused)              0       0     0   5     FB1_6   3     I/O     
(unused)              0       0     0   5     FB1_7         (b)     
(unused)              0       0     0   5     FB1_8   4     I/O     
(unused)              0       0     0   5     FB1_9   5     GCK/I/O 
(unused)              0       0     0   5     FB1_10        (b)     
(unused)              0       0     0   5     FB1_11  6     GCK/I/O 
(unused)              0       0     0   5     FB1_12        (b)     
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0     0   5     FB1_14  7     GCK/I/O 
(unused)              0       0     0   5     FB1_15  8     I/O     
(unused)              0       0     0   5     FB1_16        (b)     
(unused)              0       0     0   5     FB1_17  9     I/O     
(unused)              0       0     0   5     FB1_18        (b)     

Signals Used by Logic in Function Block
  1: PB               

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LED                  X....................................... 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
(unused)              0       0     0   5     FB2_2   35    I/O     
(unused)              0       0     0   5     FB2_3         (b)     
(unused)              0       0     0   5     FB2_4         (b)     
(unused)              0       0     0   5     FB2_5   36    I/O     
(unused)              0       0     0   5     FB2_6   37    I/O     
(unused)              0       0     0   5     FB2_7         (b)     
(unused)              0       0     0   5     FB2_8   38    I/O     
(unused)              0       0     0   5     FB2_9   39    GSR/I/O 
(unused)              0       0     0   5     FB2_10        (b)     
(unused)              0       0     0   5     FB2_11  40    GTS/I/O 
(unused)              0       0     0   5     FB2_12        (b)     
(unused)              0       0     0   5     FB2_13        (b)     
(unused)              0       0     0   5     FB2_14  42    GTS/I/O 
(unused)              0       0     0   5     FB2_15  43    I/O     
(unused)              0       0     0   5     FB2_16        (b)     
(unused)              0       0     0   5     FB2_17  44    I/O     
(unused)              0       0     0   5     FB2_18        (b)     
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
(unused)              0       0     0   5     FB3_2   11    I/O     
(unused)              0       0     0   5     FB3_3         (b)     
(unused)              0       0     0   5     FB3_4         (b)     
(unused)              0       0     0   5     FB3_5   12    I/O     
(unused)              0       0     0   5     FB3_6         (b)     
(unused)              0       0     0   5     FB3_7         (b)     
(unused)              0       0     0   5     FB3_8   13    I/O     
(unused)              0       0     0   5     FB3_9   14    I/O     
(unused)              0       0     0   5     FB3_10        (b)     
(unused)              0       0     0   5     FB3_11  18    I/O     
(unused)              0       0     0   5     FB3_12        (b)     
(unused)              0       0     0   5     FB3_13        (b)     
(unused)              0       0     0   5     FB3_14  19    I/O     
(unused)              0       0     0   5     FB3_15  20    I/O     
(unused)              0       0     0   5     FB3_16        (b)     
(unused)              0       0     0   5     FB3_17  22    I/O     
(unused)              0       0     0   5     FB3_18        (b)     
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
(unused)              0       0     0   5     FB4_2   24    I/O     
(unused)              0       0     0   5     FB4_3         (b)     
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   25    I/O     
(unused)              0       0     0   5     FB4_6         (b)     
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   26    I/O     
(unused)              0       0     0   5     FB4_9   27    I/O     
(unused)              0       0     0   5     FB4_10        (b)     
(unused)              0       0     0   5     FB4_11  28    I/O     
(unused)              0       0     0   5     FB4_12        (b)     
(unused)              0       0     0   5     FB4_13        (b)     
(unused)              0       0     0   5     FB4_14  29    I/O     
(unused)              0       0     0   5     FB4_15  33    I/O     
(unused)              0       0     0   5     FB4_16        (b)     
(unused)              0       0     0   5     FB4_17  34    I/O     
(unused)              0       0     0   5     FB4_18        (b)     
*******************************  Equations  ********************************

********** Mapped Logic **********


LED <= NOT PB;

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572-7-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11         XC9572-7-PC44      35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 PB                               23 GND                           
  2 LED                              24 TIE                           
  3 TIE                              25 TIE                           
  4 TIE                              26 TIE                           
  5 TIE                              27 TIE                           
  6 TIE                              28 TIE                           
  7 TIE                              29 TIE                           
  8 TIE                              30 TDO                           
  9 TIE                              31 GND                           
 10 GND                              32 VCC                           
 11 TIE                              33 TIE                           
 12 TIE                              34 TIE                           
 13 TIE                              35 TIE                           
 14 TIE                              36 TIE                           
 15 TDI                              37 TIE                           
 16 TMS                              38 TIE                           
 17 TCK                              39 TIE                           
 18 TIE                              40 TIE                           
 19 TIE                              41 VCC                           
 20 TIE                              42 TIE                           
 21 VCC                              43 TIE                           
 22 TIE                              44 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572-7-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : HIGH
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : OFF
Global Set/Reset Optimization               : OFF
Global Ouput Enable Optimization            : OFF
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25

I've just noticed the xsvf file seems to be 0 bytes(!) What's the right method for generating one?

[guzunty]

Er, yes. A zero byte xsvf file is not good.

To produce the xsvf file, you use the Impact tool. There is a way to do it more easily from the command line, but let's stick with the tried and tested method...

* In ISE: Tools > Impact
* In Impact: File > New Project > Choose Yes
* Choose Prepare a Boundary Scan File
* In the dropdown below choose XSVF, click OK
* Choose or enter the name of the xsvf file to be created and click 'Save'
* Dismiss warning dialog
* Select the .jed file you want to program and click 'Open'
* Select the CPLD chip icon.
* Operations > Program, click OK
* Dismiss warning dialog
* Message 'Program Succeeded'.
* Output > XSVF File > Stop writing file

File is ready for programming, transfer to Raspberry Pi and use gz_load.

File size for most cores is around 53K

HTH,

Derek

[DaveTheWalker]

Well, I followed this guide to make an xsvf file and got one with about 101kB:

http://dangerousprototypes.com/docs/Exp ... SE_Webpack
(and actually, it's the same as your method)

but I get this error message:

• pi@raspberrypi:~/Dave/guzunty$ sudo gz_load in1_out2.xsvf
  Guzunty loader v5.01, portions courtesy Xilinx, Inc.
  XSVF file = in1_out2.xsvf
  ERROR: TDO mismatch and exceeded max retries
  ERROR at or near XSVF command #8. See line #8 in the XSVF ASCII file.
  ERROR: TDO mismatch and exceeded max retriesExecution Time = 0.060 seconds

[guzunty]

That file size definitely looks wrong.

Please check that you are targeting the correct chip in the ISE tool.

I just checked your fitter report. You are indeed targeting the wrong chip.

It is confusing I know but there are two different chips with very similar names. You chose the XC9572-PC44 which is the wrong one, sorry.

You need to target the XC9572XL-PC44. To fix this, click the little chip with red tick mark on it on the left hand side of the ISE interface. Change the 'Family' and 'Device' fields. Then rerun the Synthesis process and the Impact procedure above.

Why Xilinx did this I have no idea. Quite a few people have fallen into this trap. The non XL variant of the device does not even use the same supply voltage!

[DaveTheWalker]

Woohoo!

It works now. You're a genius Thanks for helping me to get my "Hello World" inverter off the ground - I really appreciate it.

Cheers,
Dave

[DaveTheWalker]

Quick additional query - when driving a clocked core, do I need to bridge JP11 so that GCK1 can get across?

If not, how do I clock it?

If so, how does gz_test work without this link??

Many thanks,
Dave

[guzunty]

Hi Dave,

Since many cores need a clock, link JP11 is made by default. To enable the clock for your own project, just turn on the RPi hardware clock on GPIO4. Ensure that the core is built so that the clock is coming in on the correct pin (GCLK1). The source for gz_test shows how all this is done. The ucf file shows how to use the BUFG constraint and the gz_test.c file shows how to enable the RPi clock.

[texy]

The only wiring diagram I have is a schematic for the daughter board I have coming in a few more days.

However, it's not too hard to wire from a table:

Code: Select all

LCD Module        Guzunty
D0 thru D15->FB1_2 thru FB3_9 (P1)
CS->FB3_11 (P1)
WR->FB3_14 (P2)
RESET->FB3_15 (P2)
CD (RS)->FB3_16 (P2)
ENA (RD)->FB3_17 (P2)

You also need to make JP15 on the underside of the board with a solder bridge, or you can instead connect Pin 26 of the Pi GPIO connector to FB4_MC5 if you built with a long pin GPIO header on the Guzunty.

Hi,
I have wired the Guzunty to the display as outlined in this post and bridged JP15.
I downloaded and programmed the CPLD from here :
https://github.com/Guzunty/Pi/tree/master/src/gz_lcd
I have configured the module as in a previous post :

Code: Select all

sudo modprobe fbtft_device name=sainsmart32spifb
sudo modprobe sainsmart32fb

...but all I get is a white screen. Any idea's ?

I am unsure what to do with JP1, 2, 3 & 4. Do they need to be on one side to program, but then move them to the other to run ????
Texy

[guzunty]

Try this:

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sudo modprobe fbtft_device name=sainsmart32spifb gpios=reset:4,dc:7 rotate=3 verbose=0 speed=32000000 fps=30
sudo modprobe sainsmart32fb

[texy]

Thanks - all working now

Texy

[guzunty]

Great to hear.

As far as the four jumpers are concerned, you don't need to move them unless you need to max out the number of signals available to your project.

Those jumpers allow the Pi signals used for programming the CPLD to be repurposed once the device is programmed and working the way you want. The CPLD retains its program for 20 years unless you reprogram it to do something else.

Now you can duplicate my SPI bus speed experiments. I'm not sure Notro believes me

best,

Derek