I'm building an I2S driver, which is almost okay, but I'm now going a bit further and trying to add some new format. For now it's only 48kHz 32bits, which is pretty exotic ahah.
So I do want to have 48kHz 16bits and also 44.1kHz 16bits and 32 bits.
BUT when I'm trying to generate the clock I have some trouble with 44.1kHz, I've tried to generate it with the OSC @19.2MHz but the result were bad, so I used the 500MHz of PLLD, but the results are also bad, I have BCK = 2.8242MHz, and LRCK = 43.4503kHz, which is pretty bad.
BCK should be : 2822400 Hz
and LRCK 44100Hz
I set MASH 1 , DIVI = 177 , DIVF = 158 , which from my calculation should give me BCK = 2822398,377 Hz and LRCK = 44099,9746 Hz , but that obviously not what I do have, and I'm wondering if there's any way to have better results.
May be this is okay but I was thinking that the 500Hz missing might be a problem. Is there other solutions? Is it a problem ?