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How do I well set PLLD?

Fri Jun 16, 2017 2:40 pm


I'm building an I2S driver, which is almost okay, but I'm now going a bit further and trying to add some new format. For now it's only 48kHz 32bits, which is pretty exotic ahah.
So I do want to have 48kHz 16bits and also 44.1kHz 16bits and 32 bits.

BUT when I'm trying to generate the clock I have some trouble with 44.1kHz, I've tried to generate it with the OSC @19.2MHz but the result were bad, so I used the 500MHz of PLLD, but the results are also bad, I have BCK = 2.8242MHz, and LRCK = 43.4503kHz, which is pretty bad.

BCK should be : 2822400 Hz
and LRCK 44100Hz

I set MASH 1 , DIVI = 177 , DIVF = 158 , which from my calculation should give me BCK = 2822398,377 Hz and LRCK = 44099,9746 Hz , but that obviously not what I do have, and I'm wondering if there's any way to have better results.

May be this is okay but I was thinking that the 500Hz missing might be a problem. Is there other solutions? Is it a problem ?



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Re: How do I well set PLLD?

Tue Jan 16, 2018 3:42 am

There's an error in the BCM2835 Peripherals datasheet. The denominator for the fractional part of the clock divisors is 4096, not 1024. I checked your values and 500/(177+158/4096)=2.82423, while 500/(177+632/4096)=2.822398, your target.

See https://elinux.org/BCM2835_datasheet_errata#p105_table

Edit: Also, how are you generating 44.1 kHz from 500 mHz when the clock divisor can be, at most, 4095+4095/4096?
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Posts: 243
Joined: Fri Jun 10, 2016 3:18 pm

Re: How do I well set PLLD?

Wed Jan 17, 2018 4:23 pm

Hi there,

As you can see this post is from a while ago. But I think this thread can help :


The part in the I2S sound thread where we spoke about that issue:

if not I can look into old notes, but from what I remember you can set the divisor as a float. Even though I don't remember exactly how there's a register you have to set to go to Float division and then you can also set INT part and FLOAT part, so that you can divide the original clock by almost whatever you'd like.


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