I've made a new branch until this is fixed, here.snazbaz wrote:....
Please try to build and check if the problem still occurs.
EDIT: i've not actually tried to build this, so maybe hold off for a minute while i build first.
EDIT 2: Ok it builds.
I've made a new branch until this is fixed, here.snazbaz wrote:....
Ah now that's interesting!6by9 wrote: What firmware are you running? "vcgencmd version". There was a fix required for video_encode (https://github.com/raspberrypi/firmware/issues/728), so rpi-update between 30 Dec and 13 Feb will stall in video_encode after a while
Code: Select all
:~# vcgencmd version
Feb 8 2017 19:13:43
Copyright (c) 2012 Broadcom
version d6903a3d6a6dbcc3c03e8ec6facb1af2883951c9 (clean) (release)
Ok the code in the new branch linked above builds fine. let me know how you get on.snazbaz wrote:..
That'll almost certainly be the cause then. It was a FIFO wrap issue that stalled if the encoded frame split around the wrap point in a very particular manner.snazbaz wrote:Ah now that's interesting!6by9 wrote: What firmware are you running? "vcgencmd version". There was a fix required for video_encode (https://github.com/raspberrypi/firmware/issues/728), so rpi-update between 30 Dec and 13 Feb will stall in video_encode after a while
I'll do an update and see if the problem goes away.Code: Select all
:~# vcgencmd version Feb 8 2017 19:13:43 Copyright (c) 2012 Broadcom version d6903a3d6a6dbcc3c03e8ec6facb1af2883951c9 (clean) (release)
Good news! I wouldn't have caught that bug, glad 6by9 let us know.snazbaz wrote:It's looking like the firmware bug was the culprit, first test run since updating and it's already been going over 1 hour now which would have been unusual beforehand!
I'll keep it running overnight and do some more testing, thanks for the pointers guys!
This is one of the key things 6by9/Orbital6's raspi_tc358743 custom build will sort out for you, sending the soft reset when initialising.curiouscat wrote: If I try to re-launch raspivid more than once I get a the "No data received from sensor." error.
You don't need todo anything physical, but you probably will have to change i2c-0 to i2c-1 if that's where the appropriate device is on your Pi.curiouscat wrote:Wow. So If I understand this; I need to setup second physical i2c link (first being existing flex) between PI3 GPIO and b101 bridge. Download raspi_tc358743.c and update its line i2c_fd = open("/dev/i2c-0", O_RDWR); to i2c_fd = open("/dev/i2c-1", O_RDWR); . Compile it and execute it with the proper combination of options.
Will this executable work with the uv4l vid streamer?
Is there a diagram for the i2c link?
Using raspivid or UV4L to talk to a B101 is using unsupported code. It was written for a demo and no changes will be forthcoming for it.curiouscat wrote:Wow. So If I understand this; I need to setup second physical i2c link (first being existing flex) between PI3 GPIO and b101 bridge. Download raspi_tc358743.c and update its line i2c_fd = open("/dev/i2c-0", O_RDWR); to i2c_fd = open("/dev/i2c-1", O_RDWR); . Compile it and execute it with the proper combination of options.
Will this executable work with the uv4l vid streamer?
Is there a diagram for the i2c link?
I can speak for UV4L. It should be possible to implement the resetting feature for the B101 to work in UV4L and will very likely be done in the future (I cannot say when though).curiouscat wrote:I plan on implementing raspi_tc358743.c at some point over the next couple of days but the statement "control code running on the ARM (not the GPU)" got me wondering what is meant by control code. Does this include image processing and if so would you expect the split memory setting to be lower vs what was used for uv4L or are we talking some other specific control like the interaction control settings/functions of the tc358743 and would not impact split memory setting?
The toshiba resets fine already, it's just that you need to reset video tx buffer in register 4 which was missed out of raspivid but is added in my repo linked previously. Writing a 0x0000 to 0x4 after you wake the toshiba up at the start of an init is enough.RpiName wrote: I can speak for UV4L. It should be possible to implement the resetting feature for the B101 to work in UV4L and will very likely be done in the future (I cannot say when though).
Ok, thanks.Orbital6 wrote:The toshiba resets fine already, it's just that you need to reset video tx buffer in register 4 which was missed out of raspivid but is added in my repo linked previously. Writing a 0x0000 to 0x4 after you wake the toshiba up at the start of an init is enough.
I will double check next time to make sure that at the end playback the tosh is being put to sleep.RpiName wrote:Ok, thanks.Orbital6 wrote:The toshiba resets fine already, it's just that you need to reset video tx buffer in register 4 which was missed out of raspivid but is added in my repo linked previously. Writing a 0x0000 to 0x4 after you wake the toshiba up at the start of an init is enough.
UV4L has some support because the firmware has some code for it, and therefore the standard camera component sees it. That code is not supported and will not be fixed if it breaks. It's also limited to only 720p input.curiouscat wrote:Any idea of the pros and cons of raspi_tc358743.c vs UV4L (as it appears there is still some support for UV4L)?
UV4L no as above.At some point I would like to scale this project up to the PI3 compute with the four lane CSI-2 so I can go up to the 1080p30. Has anyone actually attempted this yet? Will either raspi_tc358743.c or UV4L have four lane capability in the near future if not already?
isn't the csi pinout on the pi slightly slight different to what is standard? If you had a board that changed pins 8, 9, 11 and 12 to utilise 4 lanes, would the pi play ball?6by9 wrote: Raspi_tc358743 can be theoretically do 4 lane CSI if you have the b102 board. The code already switches between 1 and 2 lanes based on required pixel rate. There's no way to do it with the b101 board.
The Pi is different to what standard? There isn't a standard!Orbital6 wrote:isn't the csi pinout on the pi slightly slight different to what is standard? If you had a board that changed pins 8, 9, 11 and 12 to utilise 4 lanes, would the pi play ball?
ah. you see i assumed the pinout to keep the data lanes adjacent, but pins 11 to 14 threw me off (in the linked pinout).6by9 wrote:The Pi is different to what standard? There isn't a standard!Orbital6 wrote:isn't the csi pinout on the pi slightly slight different to what is standard? If you had a board that changed pins 8, 9, 11 and 12 to utilise 4 lanes, would the pi play ball?
Did you mean CM? If so then it has a 22 pin connector that does carry the extra 2 lanes.
Those two lanes arent routed out from under the SoC on a standard pi, so there really is no way to get 4 lanes to work. Pins 8&9 being the MIPI clock lane is fundamental to having a working link - you can't have 4 data lanes with no clock lane.