I have tried the wiringPi approach using the gpio terminal commands. But this time the highest frequency that is correctly set is round 2 MHz. Above that there is an error in the value, and setting a value above about 8 MHz doesn't do anything.
Also, thanks for the code pointers, though I admit I'm not fully clear what they mean. It looks like it tries difference clocks as you say ( for (c=0; c,numc; c++) and within that loop it looks like there is some truncation modulo 409, which would agree with the Broadcomm docmentation of 12 bits for DIVI and DIVF values. So it would seem that none of the PLLs as set in the standard distribution are suitable for the creation of this frequency.
As a new solution, I have tried to alter the device tree along the lines in link
, my version being:
My logic was to alter the APER div from 4 to 2 in the hope of increasing the allowable frequency output on GPCLK0.
But after compiling the .dts file and putting into /boot it seems to have no effect.
It is possible that the dt-blob.dts file is wrong. I did get many warnings from the dtc command, along the lines of
Code: Select all
/boot/bt-blob.bin: Warning (unit_address_vs_reg): Node /videocore/pins_cm/pin_defines/[email protected]_SDA has a unit name, but no reg property.
But I am now well beyond my knowledge or experience. I'm not clear whether this is a possible approach and even if it is, what is wrong with what I have tried.