Where do you think that is?
With the new timing sequence, I have:
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CLK: 000 001 002 003 004 005 006 007 | 008 009 010 011 012 013 014 015 | 016 017 018 019 020 021 022 023
MOSI: 0 0 0 0 0 1 1 chn | sel bit X X X X X X | X X X X X X X X
MISO: X X X X X X X X | X X X \0 B11 B10 B09 B08 | B07 B06 B05 B04 B03 B02 B01 B00
And consequently the code is now:
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spiData  = 0x06 | (chan >> 2); // 0b0000011X is start bit + single-mode select
// then bitor with MSB of ADC channel (0-4 or 0-7)
spiData  = chan << 6; // two MSB of second byte are last two bits of chn
spiData  = 0; // send third byte
wiringPiSPIDataRW (node->fd, spiData, 3);
return ( (spiData  & 0x0f) << 8) | spiData ;// 4 LSB of 2nd byte are 4 MSB of data
// 3rd byte is 8 LSB of data
But this is essentially the same as last time, and doesn't solve the problem—with AREF = 3v3, the values are correct, within the resolution. With AREF = 0v33, the values are 10-20 mV too high.
As an aside, I seem to be discovering the same thing itisme did: This chip does NOT like high clock speeds. Need to play around with it some more to narrow things down.
EDIT: A re-Read of The Friendly Manual revealed that nonlinearity increases dramatically with lower VREFs, especially at lower Vdd. This guy over at the Arduino forums
says he solved the nonlinearity (at least for VREF = Vdd = 5V) with a unity gain amp—something I'll learn about this year in my EE classes, perhaps? I'll look into it. In particular, the last graph he posted seems like it would explain my current problem quite neatly.
I haven't done much more with the clock speed experimentation, but from what I have done it appears that it doesn't like speeds much above 400kHz. This is based solely on the output when a channel is connected directly to VREF, which at high speeds is likely to be 4090 or 4080 or even 4030 instead of the expected 4095.