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KarlS
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Thu Jan 31, 2013 7:39 pm

Some more results. After tinkering with my SPI settings, I can now read temperature and humidity ... kind of.

The SPI settings first: normal clock speed is 8MHz, FIFO read is at 1MHz (reading at 2MHz produced too many bit errors). The RFM01 configuration is:

Code: Select all

void rfm01_init() {
  // Source: "RFM01 Universal ISM Band FSK Receiver" (http://www.hoperf.com/upload/rf/RFM01.pdf)

  rfm01_command(CMD_CONFIG |            // -------- Configuration Setting Command --------
             BAND_915 |                 // selects the 915 MHz frequency band
             LOWBATT_EN |               // enable the low battery detector
             CRYSTAL_EN |               // the crystal is active during sleep mode
             LOAD_CAP_12C5 |            // 12.5pF crystal load capacitance
             BW_134);                   // 134kHz baseband bandwidth

  rfm01_command(CMD_FREQ |              // -------- Frequency Setting Command --------
             0x07cf);                   // F = ((freq / (10*c1)) - c2) * 4000
                                         // 914.99 MHz --> F = ((915/(10*3))-30)*4000 = 0x07cf

  rfm01_command(CMD_WAKEUP |            // -------- Wake-Up Timer Command --------
             1<<8 |                     // R = 1
             0x05);                     // M = 5
                                        // T_wake-up = (M * 2^R) = (2 * 5) = 10 ms

  rfm01_command(CMD_LOWDUTY |           // -------- Low Duty-Cycle Command --------
             0x0e);                     // (this is the default setting)

  rfm01_command(CMD_AFC |               // -------- AFC Command --------
             AFC_VDI |                  // drop the f_offset value when the VDI signal is low
             AFC_RL_15 |                // limits the value of the frequency offset register to +15/-16
             AFC_STROBE |               // the actual latest calculated frequency error is stored into the output registers of the AFC block
             AFC_FINE |                 // switches the circuit to high accuracy (fine) mode
             AFC_OUT_ON |               // enables the output (frequency offset) register
             AFC_ON);                   // enables the calculation of the offset frequency by the AFC circuit

  rfm01_command(CMD_DFILTER |           // -------- Data Filter Command --------
             CR_LOCK_FAST |             // clock recovery lock control, fast mode, fast attack and fast release
             FILTER_DIGITAL |           // select the digital data filter
             DQD_2);                    // DQD threshold parameter

  rfm01_command(CMD_DRATE |             // -------- Data Rate Command --------
             0<<7 |                     // cs = 0
             0x0012);                   // R = 18
                                        // BR = 10000000 / 29 / (R + 1) / (1 + cs*7) = 18.15kbps

  rfm01_command(CMD_LOWBATT |           // -------- Low Battery Detector and Microcontroller Clock Divider Command --------
             0<<5 |                     // d = 0, 1MHz Clock Output Frequency
             0x06);                     // t = 6, determines the threshold voltage V_lb = 2.25 + t * 0.1 = 0.825V

  rfm01_command(CMD_RCON |              // -------- Receiver Setting Command --------
             VDI_CR_LOCK |              // VDI (valid data indicator) signal: clock recovery lock
             LNA_6 |                    // LNA gain set to -6dB
             RSSI_103);                  // threshold of the RSSI detector set to -103dB

  rfm01_command(CMD_FIFO |              // -------- Output and FIFO Mode Command --------
             8<<4 |                     // f = 8, FIFO generates IT when number of the received data bits reaches this level
             1<<2 |                     // s = 1, set the input of the FIFO fill start condition to sync word
             0<<1 |                     // Disables FIFO fill after synchron word reception
             0);                        // Disables the 16bit deep FIFO mode

  rfm01_command(CMD_FIFO |              // -------- Output and FIFO Mode Command --------
             8<<4 |                     // f = 8, FIFO generates IT when number of the received data bits reaches this level
             1<<2 |                     // s = 1, set the input of the FIFO fill start condition to sync word
             1<<1 |                     // Enables FIFO fill after synchron word reception
             1);                        // Ensables the 16bit deep FIFO mode

  rfm01_command(CMD_RCON |              // -------- Receiver Setting Command ---------
             VDI_CR_LOCK |              // VDI (valid data indicator) signal: clock recovery lock
             LNA_6 |                    // LNA gain set to -6dB
             RSSI_103 |                 // threshold of the RSSI detector set to -103dB
             1);                        // enables the whole receiver chain

  usleep(5000);                         // Allow crystal oscillator to start
}
This produces the following output:

Code: Select all

09:18:51 00 a0 30 03 af 01 01 80 00 00 d6 60 01 55 55 54 5b a9 40 60 07 5e 02 07 00 00 01 ac c0 02 aa aa a8
09:18:51 00 a0 30 03 af 01 01 80 00 00 d6 60 01 55 55 54 5b a9 40 60 07 5e 02 03 00 00 01 ac c0 02 aa aa a8
09:18:51 00 a0 30 03 af 01 01 80 00 00 d6 60 00 00 19 9f e0 ef c0 ca 05 cf cd c7 93 f8 1a 28 78 b5 1f e0 b8
09:19:39 00 a0 30 03 af 01 01 80 00 00 9a 20 01 55 55 54 5b a9 40 60 07 5e 03 03 00 00 01 34 40 06 aa aa a8
09:19:39 00 a0 30 03 af 01 01 80 00 00 9a 20 02 55 55 54 5b a9 40 60 07 5e 02 03 00 00 01 34 40 06 aa aa a8
09:19:39 00 a0 30 03 af 01 01 80 00 00 9a 20 00 00 28 88 10 12 3a 14 5f 3c 29 6a 35 11 bf 99 f2 6c 63 27 56
09:20:27 00 a0 30 04 2f 03 02 00 00 00 c1 80 01 55 55 54 5b a9 40 60 08 5e 04 04 00 00 01 83 00 02 aa aa a8
09:20:27 00 a0 30 04 2f 02 02 00 00 00 c1 80 01 55 55 54 5b a9 40 60 08 5e 04 0c 00 00 01 83 00 02 aa aa a8
09:20:27 00 a0 30 04 2f 03 02 00 00 00 c1 80 00 00 0f bb c7 79 d3 93 00 b8 77 91 4f fc 40 a3 e2 22 33 de 36
Now comes the tricky part. For whatever reason the data seem to be right-shifted by 1 bit. Below are the same data in binary form (and I've deleted the duplicate rows):

Code: Select all

07:52:27 00000000 10100000 00111000 00000011 10101111 10000000 11000001 00000000 00000000 00000000 ...
                               -tttttttttttt t hhhhhh h
                               <=== -0.7 ====> <= 95 =>


08:42:51 00000000 10100000 00111000 00000000 10101111 10000001 00000011 00000000 00000000 00000000 ...
                               -tttttttttttt t hhhhhh h
                               <=== -0.1 ====> <= 95 =>

09:18:51 00000000 10100000 00110000 00000011 10101111 00000001 00000001 10000000 00000000 00000000 ...
                               -tttttttttttt t hhhhhh h
                               <==== 0.7 ====> <= 94 =>

09:20:27 00000000 10100000 00110000 00000100 00101111 00000011 00000010 00000000 00000000 00000000 ...
                               -tttttttttttt t hhhhhh h
                               <==== 0.8 ====> <= 94 =>
I haven't figured out the wind speed and direction yet (the bearing was S -> SE, speed 2->5kmh) and of course no rain data. The rain bucket isn't even connected between November and March ;) Does anyone have a suggestion about the (possible) bit shift?

ksangeelee
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Thu Jan 31, 2013 8:32 pm

KarlS wrote:I haven't figured out the wind speed and direction yet (the bearing was S -> SE, speed 2->5kmh) and of course no rain data. The rain bucket isn't even connected between November and March ;) Does anyone have a suggestion about the (possible) bit shift?
Just some immediate thoughts...

The two things that come to mind are 1) FIFO overflow by the time you reach the FIFO byte (is 1MHz fast enough to get the byte before the next bit is shifted in?), and 2) the bit-rate - maybe it's quantizing the stream just on the wrong side of centre. Even with fast clock-recovery slopes, the tolerance is about 250bps (as per deltaB calculation in datasheet).

I'd consider setting FIFO to trigger on VDI rather than the synchron (just for experimentation) to see how the synchron word comes through to the FIFO (e.g. you know exactly what you expect to see). You may get deluged with noise in the FIFO, but lowering the RSSI threshold would avoid this.

I'd also focus more on the CRC8 as your test of data integrity. Does the data pass CRC8 when shifted back to the correct byte boundaries? I'd try CRC8 over bytes 0-9 and also bytes 1-9 (the most likely).

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KarlS
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Thu Jan 31, 2013 9:57 pm

ksangeelee wrote:1) FIFO overflow by the time you reach the FIFO byte (is 1MHz fast enough to get the byte before the next bit is shifted in?)
Shouldn't I see a left-shift than?
ksangeelee wrote:2) the bit-rate - maybe it's quantizing the stream just on the wrong side of centre. Even with fast clock-recovery slopes, the tolerance is about 250bps (as per deltaB calculation in datasheet)
Sorry, but that's way beyond me. I will be focussing on the CRC next.

ksangeelee
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Thu Jan 31, 2013 10:19 pm

KarlS wrote:
ksangeelee wrote:1) FIFO overflow by the time you reach the FIFO byte (is 1MHz fast enough to get the byte before the next bit is shifted in?)
Shouldn't I see a left-shift than?
I think bits would need to be right-shifted into the FIFO so they don't end up in the wrong order.
KarlS wrote:
ksangeelee wrote:2) the bit-rate - maybe it's quantizing the stream just on the wrong side of centre. Even with fast clock-recovery slopes, the tolerance is about 250bps (as per deltaB calculation in datasheet)
Sorry, but that's way beyond me. I will be focussing on the CRC next.
My knowledge is superficial on all this stuff, but I think that the data-rate is what we expect to see, the recovered clock (from the RF bit stream) is what the module actually sees, and the actual clock is effectively a combination of the two. If it doesn't line up correctly with your payload bits, then you may miss or double-count some bits.

avago
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Fri Feb 01, 2013 4:20 pm

DCF is alive and transmitting. Quite by accident I found it. Once an hour starting at about 2 minutes past the hour, I have received a time/date. I thought it was the CRC problem I was trying to solve, so didnt pay attention at first, but then noticed the CRC was correct.
I normally get say A8 C0 DD 23 00 00 02 D1 80 36 00 15 55 55,
but I got 00 B8 CA 54 03 03 13 C2 01 45 34 00 15 55 55 at around 1400 (UTC+1), on 1/2/2013
Seems to be (after CA) 54H ignore bit 2 in 1st nibble ie 14, 03, 03s, (20)13 ?2M 01D
this at around 1500 00 B8 CA 55 03 03 13 C2 01 45 DD 00 15 55 55
and 1600 tim 10, rxi-> 00 B8 CA 56 03 03 13 C2 01 45 D7 00 15 55 55
The messages arent sent after 6 minutes past, and start around 2 mins past.

In terms of SPI read I am now successfully receiving fifo on the status register at 5Mhz in 3 x bit reads, but only if I disable/enable the PIC SPI module, and it has to be via a procedure call, not inline code in the interrupt. There is something very wierd going on there, but I have lost patience trying to sort this out. Microchip have had SPI issues on older revisions on this chip (33fj128), so I'm leaving it that and ignoring the inline code bit. It's probably some 'knowledge' item, aka my lack of experience.

I have also found that you need to power cycle the module after code changes otherwise it remembers some spi settings, so you think it's all ok until the next time you turn it on! - but this could simply be the spi problem I'm having.(had)
If a man says something, and a women doesn't hear, is he still wrong?

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KarlS
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Sat Feb 02, 2013 1:42 am

avago wrote:I have also found that you need to power cycle the module after code changes
Do you think a power cycle is necessary? As I understand the manual a software reset (command '0xFF00') is equivalent to a power cycle reset.

avago
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Sat Feb 02, 2013 9:14 am

KarlS wrote:
avago wrote:I have also found that you need to power cycle the module after code changes
Do you think a power cycle is necessary? As I understand the manual a software reset (command '0xFF00') is equivalent to a power cycle reset.
On the RF12B there is only the external reset line - no soft reset. It's only a problem during development, and only whilst 'playing' with the SPI, to cure the CRC issue.

I have noticed that the hourly DCF time update is stopping the module from receiving. Anyone else got this? I'm going to try re-sending the entire RX configuration, once I realise a packet is missing. I'm getting the idea the RF12 is a PITA. :o
If a man says something, and a women doesn't hear, is he still wrong?

ksangeelee
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Sat Feb 02, 2013 2:25 pm

ksangeelee wrote:I think bits would need to be right-shifted into the FIFO so they don't end up in the wrong order.
@KarlS, I'm now sure that's wrong - I'd misunderstood part of the transmitter's datasheet. I agree, overflows would be left-shifted. Did you get to the bottom of that bit-shift issue?

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KarlS
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Sat Feb 02, 2013 7:28 pm

ksangeelee wrote:Did you get to the bottom of that bit-shift issue?
Nope. I keep changing the RFM01 configuration one tiny bit at the time, but the results are seldom what I expect. Maybe the problem is not so much the RFM01 configurattion, but - as avago suggested - an SPI issue.

hystrix
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Sun Feb 03, 2013 12:30 pm

I have finally got my Rev2 Pi receiving data! :D

I'm sure I need to do a bit more tweaking....I'm not consistently reading transmitted data (many minutes between successful data received), and also have quite a few crc fails....

Code: Select all

Pulse stats: Hi: 702 - 995   Lo: 1015 - 2179  (88 point)
Data bits = 88   (offset 8) (4136 short) Packet signature found
Frequency deviation 0.0KHz (0)
af 81 c4 56 00 02 01 ff 0c 58 crc fail (gap 48s)
Pulse stats: Hi: 678 - 950   Lo: 1004 - 2180  (88 point)
Data bits = 88   (offset 8) (4247 short) Packet signature found
Frequency deviation 0.0KHz (0)
af 81 e4 56 01 04 01 ff 04 3a crc ok (gap 48s)
Pulse stats: Hi: 517 - 997   Lo: 1001 - 1935  (88 point)
Threshold now 999
Temperature: 19.0C
Pressure p0 (sea level): 1035.6 hPa
Station Id: 0AF8
Temperature: 8.4C, Humidity: 86%
Wind speed: 0.34 m/s, Gust Speed 1.36 m/s, E
Wind speed: 0.8 mph, Gust Speed 3.0 mph, E
Total rain: 153.3 mm
Listening for transmission
Data bits = 88   (offset 8) (4247 short) Packet signature found
Frequency deviation 1.0KHz (1)
af 81 e5 56 03 01 01 ff 0a c0 crc fail (gap 48s)
Pulse stats: Hi: 339 - 937   Lo: 1039 - 1933  (88 point)
Data bits = 88   (offset 0) (4317 short) No packet signature found
Pulse stats: Hi: 560 - 998   Lo: 1003 - 2109  (88 point)
Data bits = 88   (offset 69) (4317 short) Packet signature found
Frequency deviation -1.0KHz (-1)
a1 59 59 43 a0 6a 83 ff ff 2a crc fail (gap 48s)
Pulse stats: Hi: 603 - 970   Lo: 1051 - 2190  (88 point)
Data bits = 88   (offset 8) (4554 short) Packet signature found
Frequency deviation 0.0KHz (0)
af 81 e7 56 04 07 01 ff 08 1d crc ok (gap 96s)
Pulse stats: Hi: 679 - 972   Lo: 1728 - 2038  (88 point)
Threshold now 1350
Temperature: 19.4C
Pressure p0 (sea level): 1035.6 hPa
Station Id: 0AF8
Temperature: 8.7C, Humidity: 86%
Wind speed: 1.36 m/s, Gust Speed 2.38 m/s, S
Wind speed: 3.0 mph, Gust Speed 5.3 mph, S
Total rain: 153.3 mm
Listening for transmission
Data bits = 87   (offset 8) (4555 short) Packet signature found
Pulse stats: Hi: 714 - 1182   Lo: 1785 - 4455  (87 point)
Data bits = 86   (offset 8) (4621 short) Packet signature found
Pulse stats: Hi: 738 - 1035   Lo: 1730 - 4456  (86 point)
Pulse stats: Hi: 690 - 1042   Lo: 1712 - 8478  (47 point)
Data bits = 86   (offset 8) (4679 short) Packet signature found
Pulse stats: Hi: 737 - 1001   Lo: 1713 - 4334  (86 point)
Data bits = 85   (offset 8) (4722 short) Packet signature found
Pulse stats: Hi: 742 - 1065   Lo: 1763 - 4465  (85 point)
Pulse stats: Hi: 732 - 1323   Lo: 1749 - 9614  (45 point)
Data bits = 86   (offset 8) (4931 short) Packet signature found
Pulse stats: Hi: 675 - 1154   Lo: 1744 - 4554  (86 point)
Data bits = 87   (offset 8) (5078 short) Packet signature found
Pulse stats: Hi: 702 - 1144   Lo: 1752 - 3533  (87 point)
Data bits = 83   (offset 8) (5078 short) Packet signature found
Pulse stats: Hi: 673 - 1010   Lo: 1684 - 4738  (83 point)
Data bits = 87   (offset 8) (5151 short) Packet signature found
Pulse stats: Hi: 628 - 1034   Lo: 1661 - 3344  (87 point)
Data bits = 88   (offset 8) (5329 short) Packet signature found
Frequency deviation 0.0KHz (0)
af 81 eb 55 02 04 01 ff 0a ba crc ok (gap 384s)
Pulse stats: Hi: 631 - 1305   Lo: 1675 - 2162  (88 point)
Threshold now 1490
Temperature: 20.0C
Pressure p0 (sea level): 1035.4 hPa
Station Id: 0AF8
Temperature: 9.1C, Humidity: 85%
Wind speed: 0.68 m/s, Gust Speed 1.36 m/s, SW
Wind speed: 1.5 mph, Gust Speed 3.0 mph, SW
Total rain: 153.3 mm
Listening for transmission
Data bits = 88   (offset 8) (5331 short) Packet signature found
Frequency deviation 0.0KHz (0)
af 81 eb 55 01 02 01 ff 0a f7 crc ok (gap 48s)
Pulse stats: Hi: 707 - 1179   Lo: 1691 - 2214  (88 point)
Threshold now 1435
Temperature: 20.0C
Pressure p0 (sea level): 1035.4 hPa
Station Id: 0AF8
Temperature: 9.1C, Humidity: 85%
Wind speed: 0.34 m/s, Gust Speed 0.68 m/s, SW
Wind speed: 0.8 mph, Gust Speed 1.5 mph, SW
Total rain: 153.3 mm
Listening for transmission
Data bits = 77   (offset 0) (5460 short) No packet signature found
Pulse stats: Hi: 740 - 1260   Lo: 1809 - 5078  (77 point)
Data bits = 83   (offset 8) (5638 short) Packet signature found
Pulse stats: Hi: 785 - 1326   Lo: 1802 - 4600  (83 point)
Pulse stats: Hi: 855 - 1232   Lo: 1888 - 4629  (49 point)
The other problem is that my frequently Pi freezes while trying to receive data (and the LED is on)...any ideas?

This is definitely a project that requires some perseverance!

mcrossley
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Sun Feb 03, 2013 2:10 pm

Kevin

Following on from your blog page...

Here are some pictures of my 868MHz transmitter.
Front
Back

The RF chip is labelled Si4021 - A Silcon Labs FSK unit.

I haven't had a chance to take any pictures of the base unit yet.

Cheers
Mark

ksangeelee
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Sun Feb 03, 2013 10:03 pm

hystrix wrote:I'm sure I need to do a bit more tweaking....I'm not consistently reading transmitted data (many minutes between successful data received), and also have quite a few crc fails....
...
The other problem is that my frequently Pi freezes while trying to receive data (and the LED is on)...any ideas?
Well done. That data looks good, just the rssi/lna/bandwidth choice that needs some tweaking. Make a note of your current settings and tweak the values. You'll need to do this again if you move the transmitter/Pi, because the settings reflect a 'sweet spot' where the signal's just right to enable an FSK receiver to decode a meaningful OOK signal.

When you say the Pi freezes, do you mean hardware crash, or just no output? If hardware crash and you're doing I2C stuff via hardware registers, then check that the i2c_bcm2708 & i2c-dev modules aren't loaded (which are only needed if you're using the /dev/i2c approach).

If you're just getting no output, then be aware that the software loops continuously looking for a valid packet of data - when it gets it, it falls back to looking every 48 seconds. However, if it fails to get the next packet, it reverts to the continuous loop looking again for a valid signal.

Also, you may want to 'diff' the original code with your current version, and make sure that all of the rev-2 changes are correct - when tweaking and hacking code, it's easy for things to creep in that you never intended to keep (esp. when messing with hardware registers through /dev/mem!).

ksangeelee
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Mon Feb 04, 2013 1:16 pm

mcrossley wrote:The RF chip is labelled Si4021
Hi Mark, can you find out what pin 16 on the Si4021 connects to? The 4 x 2 pins don't seem to correspond to an RFM02 pinout (e.g. SDI and SCK aren't in the same column).

My guess is that FSK goes via the header, down to the MCU, and that this pin will be used to generate the data signal. If so, any chance you could hook up panalyzer or similar to get a trace of the pulses? Alternatively, a voltmeter should show (close to) zero for 48 seconds, before jumping briefly if pulses are being sent.

The FSK pin is what you could piggyback onto if you want to use another transmitter to send the data.

mcrossley
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Mon Feb 04, 2013 1:44 pm

Pin 16 goes straight to the MCU 'blob' - give me a week or two to get Panalyzer running! :lol:

ksangeelee
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Mon Feb 04, 2013 6:11 pm

mcrossley wrote:Pin 16 goes straight to the MCU 'blob' - give me a week or two to get Panalyzer running! :lol:
Straight to, or via a PCB pad and a solder bridge? I can't quite make out some of the tracks in the photo.

Since you've some doubts as to whether your kit is working properly, you might want to try the voltmeter to at least see that something is being sent before embarking on Panalyzer. You may be best to figure out exactly what's not working in the existing kit.

Also, be aware that, even if the FSK pin is being modulated, it will likely require a microcontroller if you want to rework the transmitter. This would sample the FSK pin, decode the bits, and then send them via whatever transmitter you decide on. Trivial in principle, but potentially a steep learning curve if you've not done this stuff before. The devil's in the detail, and you might find it more effort than justified by the rewards - depends a lot on your disposition!

mcrossley
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Mon Feb 04, 2013 6:36 pm

I was just composing a reply to my own message, it does go via the header, but you are correct the header doesn't seem to corresponds with to the RFM02 DIP layout. Odd, but it seems to be the same IC as the RFM02, I'll try the DMM later tonight...

mcrossley
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Tue Feb 05, 2013 10:18 pm

OK, the FSK line did pulse with DMM, but when I put the soundcard OSC on it that's all it was, a simple pulse. The SDI line does carry a data burst with each transmit, I have recorded one burst as a WAV file, the quality isn't brilliant but does anyone know of any software that will do logic analysis on .wav files?

ksangeelee
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Tue Feb 05, 2013 10:43 pm

mcrossley wrote:OK, the FSK line did pulse with DMM, but when I put the soundcard OSC on it that's all it was, a simple pulse. The SDI line does carry a data burst with each transmit...
The SDI data could just be the 0xC0nn command to wake up the transmitter. If SCK is low during the SDI data burst, then SDI contains the data to transmit, otherwise SDI contains a command (Si4021 datasheet, page 20).

mcrossley
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Tue Feb 05, 2013 11:02 pm

The screen grab below shows SDI (Green) and SCK (Red), I haven't worked out the polarity yet, but it looks like the data is being sent on the SDI line?
scope.gif
scope.gif (47.15 KiB) Viewed 5081 times
This image shows the full data stream on SDI.
burst.gif
burst.gif (21.74 KiB) Viewed 5081 times

avago
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Wed Feb 06, 2013 9:54 am

There's a couple of odd things going on with that trace. 1. voltage levels of SDI should be constant. . 2. SCK should be changing state for every transition of SDI. I can only see 1 transition on SCK, at 18ms, which works out at a clock rate of 1/(18x2) = 28Hz.

Hmm. I think we're looking at aliasing - where the input frequency (SCK/SDI) is very much larger than the sampling frequency (of the sound card) Ignoring that though, SCK should be moving with SDI. What do you get on SDO?

You should not need this with SPI, but try a 10k pull up on SDI to see if those voltage levels equal out. You could be missing some of the data at the moment. Have you tried swapping SDI/SDO?
If a man says something, and a women doesn't hear, is he still wrong?

mcrossley
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Wed Feb 06, 2013 10:00 am

I will take a look, bear in mind, that this transmitter is faulty in some way...

avago
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Wed Feb 06, 2013 10:12 am

So maybe the SPI driver has failed on-board. Without SCLK you aren't going very far! As a test, I've just put a 5MHz signal through a 1M sampling scope. It missed most of it, and what was left came out at 1Hz.
Try the pull up.
If a man says something, and a women doesn't hear, is he still wrong?

mcrossley
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Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Wed Feb 06, 2013 10:42 am

My soundcard OSC has a max sampling rate of 44kHz!

Is there are ready built SD card image with Panalyser incorporated anywhere?

avago
Posts: 14
Joined: Mon Jan 28, 2013 9:20 pm

Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Wed Feb 06, 2013 10:53 am

There does seem to be on the this forum somewhere - google 'Panalyser SD' but then I cant track it down. Make sure you spell it correctly!
If a man says something, and a women doesn't hear, is he still wrong?

ksangeelee
Posts: 192
Joined: Sun Dec 25, 2011 5:25 pm
Location: Edinburgh, UK
Contact: Website

Re: Fine Offset WH1081 (Maplin N96GY) sensors working on Pi

Wed Feb 06, 2013 9:30 pm

avago wrote:SCK should be changing state for every transition of SDI
There's a mode of operation (see Si4021 datasheet, page 20) that uses SDI to receive data for transmission (breaking SPI conventions). In this case, SCK must not transition while data is being sent on SDI.

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