chunjonas
Posts: 4
Joined: Sun Jul 06, 2014 8:25 pm

what is memory barrier

Sat Jul 19, 2014 6:47 pm

Hi,

i am reading the document of BCM 2835. And a word stopped me reading further, it is said:
"
A memory write barrier before the first write to a peripheral.
A memory read barrier after the last read of a peripheral.
"
i am not clear what is a memory barrier instruction? can somebody make me clearer about this?

Thanks for answers

chun


kkp
Posts: 2
Joined: Fri Dec 30, 2011 10:09 pm

Re: what is memory barrier

Sun Jul 20, 2014 1:13 pm

For ARMv6, which is what the raspi is, you go through CP15 to create barriers:

Code: Select all

//memory barriers for ARMv6. These 3 are special and non-privileged.
#ifndef barrierdefs
 #define barrierdefs
 //raspi is ARMv6. It does not have ARMv7 DMB/DSB/ISB, so go through CP15.
 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7,  c5, 4" : : "r" (0) : "memory")
 #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory")
 //ARMv6 DSB (DataSynchronizationBarrier): also known as DWB (drain write buffer / data write barrier) on ARMv5
 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory")
#endif
//use dmb() around the accesses. ("before write, after read")
You will want to use dmb() almost everywhere the barrier is needed. The exception to this is when you wish to do clockcycle-based busyloop-delays:

If you have just done a write to gpio, the write sits in the write buffer of the arm, and will go out on the bus when possible. It has not taken effect and set the pin yet. If you merely do DMB(), the write still sits in the write buffer. You then do the busy loop, and another write to clear the pin. Now you can have two back-to-back writes sitting in the write buffer, meaning you do not get the minimum pulse width you want. So before starting busy loops, do DSB() to stall the cpu until the first write has actually gone all the way to the destination.

Code: Select all

void bdelay(unsigned n)
{
  dsb(); //force writes to have retired before the delay timer starts
  while (n) {
    asm volatile ("nop\n");
    --n;
  }
  dmb();
}
oid gpio_setpin(int pin, int lev) //only 0..31 !
{
  unsigned mask=1<<(pin&31);
  dmb(); //after read, before write
  if (lev)
    bcm2835.gpio->set[0]=mask;
  else
    bcm2835.gpio->clr[0]=mask;
}

int gpio_getpin(int pin) //only 0..31 !
{
  unsigned n;
  n=bcm2835.gpio->lev[0];
  dmb(); //after read, before write
  if (n&(1<<pin)) return 1;
  return 0;..
}

/Kasper

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ab1jx
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Re: what is memory barrier

Sat Jul 22, 2017 2:55 pm

kkp wrote:For ARMv6, which is what the raspi is, you go through CP15 to create barriers:
That was in 2014 for I'm not sure which model Pi. I thought the Pi 3 was an ARMv7? It seems to still work on my Pi 3.

Also for any newbie blindly copying code,
oid gpio_setpin(int pin, int lev) //only 0..31 !
should probably be
void gpio_setpin(int pin, int lev) //only 0..31 !
Wouldn't compile that way. I do that a bunch too.

jahboater
Posts: 5049
Joined: Wed Feb 04, 2015 6:38 pm

Re: what is memory barrier

Sat Jul 22, 2017 2:59 pm

ab1jx wrote: That was in 2014 for I'm not sure which model Pi. I thought the Pi 3 was an ARMv7? It seems to still work on my Pi 3.
The Pi3 and the new Pi2 are ARMv8

1dot0
Posts: 430
Joined: Mon Nov 28, 2016 12:31 pm

Re: what is memory barrier

Sun Jul 23, 2017 8:09 am

I also read it's a ARMv8, but I also read about ARM53 for the Pi3 (and new Pi2) - just curious about what's true and what's the difference in case.

(edited, typos)
Last edited by 1dot0 on Sun Jul 23, 2017 8:34 am, edited 1 time in total.

jahboater
Posts: 5049
Joined: Wed Feb 04, 2015 6:38 pm

Re: what is memory barrier

Sun Jul 23, 2017 8:22 am

1dot0 wrote:I also read it's a ARMv8, but I also read about ARM53 for the Pi3 (and new OPi2) - just curious about what's true and what's the diffeence in case.
The CPU name is Cortex-A53
It is ARMv8 architecture and can support both AArch64 and the 32-bit modes (A32 and T32).
It has the latest version of NEON (fully IEEE compliant and quad issue).

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ab1jx
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Location: Heath, MA USA
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Re: what is memory barrier

Sat Feb 09, 2019 7:29 pm

jahboater wrote:
Sun Jul 23, 2017 8:22 am
1dot0 wrote:I also read it's a ARMv8, but I also read about ARM53 for the Pi3 (and new OPi2) - just curious about what's true and what's the diffeence in case.
The CPU name is Cortex-A53
It is ARMv8 architecture and can support both AArch64 and the 32-bit modes (A32 and T32).
It has the latest version of NEON (fully IEEE compliant and quad issue).
But interestingly, if you load a 64 bit operating system that number after the v changes. It's like a USB mode switch a little. Tried it for a few months, came back to Raspbian. 64 bit has disadvantages too, like all the pointers are twice as big. And no omxplayer or /opt/vc stuff.

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Paeryn
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Location: Sheffield, England

Re: what is memory barrier

Sat Feb 09, 2019 11:27 pm

ab1jx wrote:
Sat Feb 09, 2019 7:29 pm
jahboater wrote:
Sun Jul 23, 2017 8:22 am
1dot0 wrote:I also read it's a ARMv8, but I also read about ARM53 for the Pi3 (and new OPi2) - just curious about what's true and what's the diffeence in case.
The CPU name is Cortex-A53
It is ARMv8 architecture and can support both AArch64 and the 32-bit modes (A32 and T32).
It has the latest version of NEON (fully IEEE compliant and quad issue).
But interestingly, if you load a 64 bit operating system that number after the v changes. It's like a USB mode switch a little. Tried it for a few months, came back to Raspbian. 64 bit has disadvantages too, like all the pointers are twice as big. And no omxplayer or /opt/vc stuff.
That's because ARMv8 is the first version which supports AArch64 so for 64-bit Linux it reports ARMv8, however the A53's also have AArch32 to provide full backwards compatibility with ARMv7, so 32-bit Linux reports it as ARMv7 as to all intents and purposes it is. Programs that know about v8 can always query the Instruction Set Attribute Registers to see if the new v8 instructions (e.g. LDA) are supported.
She who travels light — forgot something.

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