anonab
Posts: 3
Joined: Mon May 13, 2019 10:57 pm

SPI Interface Modificatoins

Mon May 13, 2019 11:43 pm

Hi,

I am using the RPI 3 B+ as a master and communicating to a slave through SPI.
The message sequence from the slave has a couple rules:

1. The Raspberry Pi needs to ensure that there is a delay of 2 SPI clocks between CS going low and start of SPI clock.
2. Raspberry PI (Host) needs to make sure that the CS is toggled every 16 bits of transfer
3. SPI word length should be 16 bits

Using the BCM2835 library given by https://www.airspayce.com/mikem/bcm2835/ and/or WiringPI I have realized that the SPI protocol does not actually toggle the CS until all the bits are delivered (sometimes I have to transfer more than 16 bits). Also, each SPI CLK cycle is only 8 bits long instead of 16.

Besides writing my own driver to accommodate for those bottlenecks or hacking my way using the current bcm2835 library. Are there any other drivers I can use that are open source?

Thanks!

User avatar
joan
Posts: 14019
Joined: Thu Jul 05, 2012 5:09 pm
Location: UK

Re: SPI Interface Modificatoins

Tue May 14, 2019 8:37 am

CS is set low before the SPI transfer and set high afterwards.

So if you want to transfer 16 bits just send 2 bytes.

As to the 2 SPI clock delay I doubt there is much to be done in an accuracy sense. There is no way you are going to reliably time 2 SPI clocks for any but low bit rates.

BBUK
Posts: 141
Joined: Tue Dec 18, 2012 10:34 am

Re: SPI Interface Modificatoins

Tue May 21, 2019 6:13 pm

@anonab
Doing what you what should be possible by introducing a function in your code that replicates one of the ones in the bcm2835 library but with minor changes to lengthen the SPI CS.

Have a look at the bcm2835_spi_transfernb function here: https://github.com/janne/bcm2835/blob/master/bcm2835.c (this is NOT the official repository, I have just linked it for convenience). As I understand it this line makes the CS active:

Code: Select all

bcm2835_peri_set_bits(paddr, BCM2835_SPI0_CS_TA, BCM2835_SPI0_CS_TA);


You could insert a short 2 cycle delay after this to ensure that the CS is at least this long before the transfer begins.

I have assumed that your SPI device does not need an exact 2 cycle CS period but one that is at least that long.

To toggle CS every 16 bits will be easy, send 2 bytes in a single transaction just as joan says

Some experimentation may be needed(!)

BBUK

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