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FET Source-Gate Charge & Back-current

Tue Dec 10, 2013 4:46 pm


I'm planning to use a MOSFET driven from a GPIO pin, with an applied software-PWM signal.
FETs require some charge at source-gate to open the source-drain flow, my actual MOSFET needs about 14 nC. When I set the GPIO high, the FET draws the required current, and when I set it low, it 'sends' back this current. According to Multisim analysises these are significant current spikes on both switches. The question is, will the backwards current spike damage my Pi when I turn off the FET? Note that I'm gonna use some resistors to limit the current spike to a maximum of 40mA peak @3.3V to stay withing GPIO specifications.

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Re: FET Source-Gate Charge & Back-current

Tue Dec 10, 2013 9:24 pm

I don't believe there is a risk that the Pi is damaged by the current spikes when the GPIO pin is switching, as long as you use a resistor between the GPIO pin and the Gate to limit the peak current. the GPIO circuitry is what is driving the current transients.
one thing to look out for is the possibility of a current transient in or out of the gate if the Drain-Source voltage changes rapidly. there is a significant Drain-Gate capacitance that will conduct a current if you apply a voltage transient to the Drain-Source pins. this current transient that flows in the Gate is not initiated by the GPIO pin circuitry so the GPIO pin voltage will be forced outside the rails (GND pin and +3.3V supply for the Pi). if you have a resistor in series with the gate you will have less peak current so your Pi may be OK. I don't know how much energy the Pi GPIO pin can take, but there is usually always "invisible" ESD protection circuitry that makes the Pi less vulnerable to ESD discharges, and this protection circuitry saves the circuit. Someone with knowledge in IC design may be able to tell us how large current spike you can inject into the pin and still be safe.

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Re: FET Source-Gate Charge & Back-current

Wed Dec 11, 2013 10:50 am

Thanks for your quick reply!
The Drain-Source voltage changes should not be a problem with simple LEDs, but DC brushed motors might generate some serious transients, since they don't draw a constant current while operating. Is that right? Additionally, the main power source is gonna be quiet stable, so it won't cause such problems. Either way, connecting the GPIO and the Pi's GND with a ~3.5V zener diode drives away the spike. I think the diode would take only a really small total energy, so a small one is enough.

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Re: FET Source-Gate Charge & Back-current

Wed Dec 11, 2013 11:58 am

The FET gate-drain capacitance and gate-source capacitance are only really of interest when the FET is in a dynamic state (i.e. switching on or off).

Ignoring drain-source dV/dT and dI/dT for now, the gate-source capacitance is charged/discharged when the gate voltage is raised/lowered. If powered from a very low impedance source (like a GPIO driver with a lot of current sourcing capability) then the inductance of the gate lead (and pcb trace to the GPIO) and the capacitance of the gate form a LC circuit, which will have a nasty tendency to ring at some large frequency (typically MHz).

If the ringing is large enough, then on turn-on/turn-off the FET will not be switched fully until some time after the driver has settled. The situation is made worse by the damped oscillation - at some point in the cycle the FET will be biased into the linear region where interesting things can happen (you may exceed the safe operational area (Ids / Vds) of the device and it will go bang).

To alleviate this, a low-value (4.7 ohm typical) resistor should be placed in-series with the gate PCB trace close to the FET gate pin. This will damp the LC circuit.

You are also correct that you need to protect the GPIO (and mosfet gate). If you have a high dV/dT application (like in motor control) then the current through the gate-drain capacitance may push the gate voltage up to a high value that either destroys the gate or the GPIO pin driving it. Fortunately, the GPIO pin is not entirely unprotected - there's an ESD protection network on it that should handle small excursions above Vdd. A beefier protection is required for the gate however - a 3.3V zener connected directly to the FET gate pin (before the 4.7 ohm resistor) should clamp adequately.

Oh and put a 10k resistor in parallel with the zener diode. This prevents a floating gate if your GPIO is unconfigured / input state.
Rockets are loud.

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