The FET gate-drain capacitance and gate-source capacitance are only really of interest when the FET is in a dynamic state (i.e. switching on or off).
Ignoring drain-source dV/dT and dI/dT for now, the gate-source capacitance is charged/discharged when the gate voltage is raised/lowered. If powered from a very low impedance source (like a GPIO driver with a lot of current sourcing capability) then the inductance of the gate lead (and pcb trace to the GPIO) and the capacitance of the gate form a LC circuit, which will have a nasty tendency to ring at some large frequency (typically MHz).
If the ringing is large enough, then on turn-on/turn-off the FET will not be switched fully until some time after the driver has settled. The situation is made worse by the damped oscillation - at some point in the cycle the FET will be biased into the linear region where interesting things can happen (you may exceed the safe operational area (Ids / Vds) of the device and it will go bang).
To alleviate this, a low-value (4.7 ohm typical) resistor should be placed in-series with the gate PCB trace close to the FET gate pin. This will damp the LC circuit.
You are also correct that you need to protect the GPIO (and mosfet gate). If you have a high dV/dT application (like in motor control) then the current through the gate-drain capacitance may push the gate voltage up to a high value that either destroys the gate or the GPIO pin driving it. Fortunately, the GPIO pin is not entirely unprotected - there's an ESD protection network on it that should handle small excursions above Vdd. A beefier protection is required for the gate however - a 3.3V zener connected directly to the FET gate pin (before the 4.7 ohm resistor) should clamp adequately.
Oh and put a 10k resistor in parallel with the zener diode. This prevents a floating gate if your GPIO is unconfigured / input state.
Rockets are loud.