Maximum current and voltage through the 40 pins before damage?

[AntonMarinski]

Is there a definitive answer to this? And is there a difference between let's say Pi 3 and Pi Zero? I can't seem to find any "confidence inspiring" information on the topic...

I know for a fact (probably) that one can draw from the 5V pins as much current as the power supply can supply.

The 3V3 pins, on the other hand? 50mA? 800mA? Each or all? Everyone claims different values.

The GPIO pins are said to handle a max of 16mA each, but no more than 50mA in total. Is this still relevant to the new Pi's that have the 40 pin layout? And they can't handle more than 3.3V, right? Is there a difference in these values depending on whether it's input or output?

I am rather confused... Any help would be greatly appreciated!
Happy almost New Year!

P.S. I know this is on the subreddit, as well. I am in quite a hurry to start prototyping my design, but without the fundamentals, rather difficult it is.

[gordon77]

Read this thread...not definitive but probably the best info we can get...

viewtopic.php?f=44&t=12498

[davidcoton]

This has been discussed before (see link above) but there is no authoratative answer.
There is no evidence that the GPIO limits apply to the 3V3 power pin (also no contrary evidence).
The 3V3 regulator was upgraded between models at some point, on the current models the regulator is capable of (IIRC) 1A. There may be constraints on 3V3 tracks between the regulator and the 3V3 pin, and we don't actually know the on-board requirement for 3V3, but in general it seems that 100mA or even 200mA should not be a problem. If you need more than that use your own 5V to 3V3 convertor -- but then the constraint will be the 5V supply and the polyfuse.

[AntonMarinski]

Read this thread...not definitive but probably the best info we can get...

viewtopic.php?f=44&t=12498

There must be a difference in the limits of the 26-pin layout and the 40-pin layout... That is my main problem. I seem to find documentation regarding only the 26-pin header and the total max of 50mA of all GPIO pins (17 pins). Therefore, ~3mA per pin. If we assume the same maximum for the now 26 GPIO's we get ~2 mA which seems absurd. To me it's illogical to increase the number of controllable pins and not raise the current maximum....

[gordon77]

Read this thread...not definitive but probably the best info we can get...

viewtopic.php?f=44&t=12498

There must be a difference in the limits of the 26-pin layout and the 40-pin layout... That is my main problem. I seem to find documentation regarding only the 26-pin header and the total max of 50mA of all GPIO pins (17 pins). Therefore, ~3mA per pin. If we assume the same maximum for the now 26 GPIO's we get ~2 mA which seems absurd. To me it's illogical to increase the number of controllable pins and not raise the current maximum....

Note the reference to 50mA per bank in the link...

[AntonMarinski]

Read this thread...not definitive but probably the best info we can get...

viewtopic.php?f=44&t=12498

There must be a difference in the limits of the 26-pin layout and the 40-pin layout... That is my main problem. I seem to find documentation regarding only the 26-pin header and the total max of 50mA of all GPIO pins (17 pins). Therefore, ~3mA per pin. If we assume the same maximum for the now 26 GPIO's we get ~2 mA which seems absurd. To me it's illogical to increase the number of controllable pins and not raise the current maximum....

Note the reference to 50mA per bank in the link...

Yeah, I just saw that. Thanks for the info. Cheers

[mahjongg]

There is no electrical difference between the limits for the 26-PIN, and 40-PIN versions of the PI, all versions of the PI essentially use the same SoC, except that a PI3 uses a SoC with a "CPU transplantation", but the rest of the chip, including the GPIO logic is the *same* for all models.
Also the polyfuse is upgraded to a higher value in the PI3, and the 3V3 regulator of the PI3 is now a switching regulator with a larger capacity.

[drgeoff]

GPIOs configured as inputs take no part in the 50 mA (or whatever the number is) total.

[mahjongg]

GPIO's configured as outputs, but outputting a '0' don't either, nor do outputs that output a '1' to a high-ohmic load.
Only if they actually source a current into a load they do.

[jojopi]

GPIO's configured as outputs, but outputting a '0' don't either, […]
Only if they actually source a current into a load they do.

So we can sink 16mA into each of the 28 GPIOs driven low, for a total of 0.458A?

No, I suspect there will be similar limits for sinking and sourcing. It may be slightly better to have a balance of the two, because sourced currents only come from the power rail within the chip and do not have to go to ground, whereas sink currents only go to ground and do have to come from the power pads.

nor do outputs that output a '1' to a high-ohmic load.

A high impedance load just means that the current will be small. You still add that current up, but it makes less difference.

[Burngate]

The way I understand it, too much voltage tends to punch through the insulation of gates, whereas too much current does its damage by over-heating elements.

If that's the case, since the output circuitry is just a half-H (two fets, one pulling up, the other pulling down) and they're going to be quite close together, heating one is going to heat the other.
So it doesn't matter which direction the current's going.

Of course this doesn't account for the per-bank limit, which (perhaps) has some sort of supply control circuit between the 3v3 input and the tops of the H.
If they've put one in the top leg of the H, why not one in the bottom leg as well?

[mahjongg]

As far as my understanding of the current limits opposed by the chips, 50mA is the safe limit for both the (accumulated) current sourced OR sunk through the metal traces inside the chip, so NO you cannot drive half an amp though these traces, and die-bond-wires.