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Clarifications on BSC slave

Posted: Wed Sep 02, 2015 3:24 pm
by krishnaiah.vv

I am curious to know who could support me w.r.t the incompleteness / bugs in BCM2835 controller documentation. My main concern is about the BSC/SPI slave chapter.

I wrote an email to Broadcom, whose response is "We don't support for BCM2835" !!!.

I might be wrong with some questions but, happy to be corrected with my understanding:)

My questions are here...
1. The polarity and phase of the clock are not clear when RPi is acting as SPI slave. The Control register(P.165) just mentions that "SPI Related" for Clk Phase and Polarity. Does it mean mode 0 of SPI i.e., Phase =0 and Polarity = 0? Shouldn't be there a defined phase and clock for SPI slaves?

2. There is no explicit FIFO register as like for Master. Docu says that reading from the lowerbyte of DR gives the data from RX FIFO and writing to Lowerbytes writes data into TX FIFO. What is the size of FIFO?

4. RX BUSY and TX BUSY flags represent what?
a) Are these flags set when the complete 8bits of byte are not received? OR
b) based on the CS line? i.e, are these flags set as long as the CS line is asserted?

3. Can some please provide the SW flow on the slave side for SPI?

It would be really if someone could clarify them..

Many thanks

Re: Clarifications on BSC slave

Posted: Wed Sep 02, 2015 4:15 pm
by jamesh
I think you need the Foundation input on this one - I'll flag up some people who may be able to help.

Re: Clarifications on BSC slave

Posted: Wed Sep 02, 2015 4:22 pm
by krishnaiah.vv
Thank you jamesh, looking forward for further steps

Re: Clarifications on BSC slave

Posted: Wed Sep 02, 2015 5:40 pm
by mahjongg
I can't help, I'm just a moderator, but Gert van Loo, has contacts with Broadcom, perhaps he can help.
By the way SPI isn't really standardized that well and things like clock-phase can differ between implementations.

Re: Clarifications on BSC slave

Posted: Wed Sep 02, 2015 6:07 pm
by krishnaiah.vv
Hi Gert van Loo, Do you have any clues on these queries?

And concerning the phase and clk, i think it is expected that slave should specify master, with which phase and clock polarities master needs to communicate(as Master generates the clock).

Re: Clarifications on BSC slave

Posted: Thu Sep 03, 2015 1:07 pm
by Gert van Loo
This question should be put to the foundation.
The reason being that to answer it I would need to have a good look at the Verilog code.
I am not sure if they can give me access without signing an NDA.
(Yes, I have had access to the code in the past and it will not have changed one bit,
but this is lawyers talking, not rational people).
James A. is very familiar with Verilog so I should think he is a good person for this.

Whilst that is going on I suggest the question is 'cleaned up' a bit.
BSC is the Broadcom equivalent of the Philips I2C interface.
But I assume that we are here talking about the SPI slave interface. (The phase of the signals against the clock in I2C is clearly specified).

I think the SPI slave interface in the datasheet then needs updating or amending.
I thought the Foundation was working on a new, improved datasheet but I have not heard anything
about that for two years.

If somebody decides it is fine to send me the Verilog code for the SPI slave interface, I will be happy to answer the question.

Re: Clarifications on BSC slave

Posted: Thu Sep 03, 2015 1:30 pm
by krishnaiah.vv
Hi Gert van Loo,

Thank you for taking the query further.
To clarify your assumptions, yes, all my queries (listed above) are related to SPI Slave which is defined as "BSC/SPI slave"( in P.160 of BCM2835_peripherals_manual).
Btw, I would be eagerly waiting for your/James A. inputs concerning the realization of SPI slave in RPi 2 Model B(40 pin header).

Hope some one allow you/us to discuss in detail on the queries.

Thank you, Krish

Re: Clarifications on BSC slave

Posted: Sat Sep 05, 2015 5:28 pm
by jdb
From our side, we can't really tell you much more (not because of NDA, but because the documentation doesn't go into any detail). The ARM peripherals datasheet is probably the best source of information despite its shortcomings.

The VPU driver isn't any help either - it's a minimal interface with no "helpful" comments about hardware/documentation inconsistencies.

The FIFO appears to be 16 entries for both read and write, however.

The clock phase and polarity bits give you four options to play with - a logic analyser will easily tell you which ones result in the correct bits coming out the other end.

Re: Clarifications on BSC slave

Posted: Mon Sep 07, 2015 12:10 pm
by krishnaiah.vv
I did the following set up and executed the test case listed below.
Both the RPis(PiA Master - PiB Slave) are connected over SPI(with common GND) as a test setup.
The issue is that, the FIFO flags in FR register doesn't set. I checked with all the 4 modes of CPHA and CPOL.

Step1 : Configured PiB as SPI slave and keep looping/waiting for data in RX FIFO using "RX FIFO Full" flag. I.e., read the data from DR only when the RX FIFO is full.
Step2 : Configured PiA as master and send some bytes of data.

In this case, the "RX FIFO full" flag doesn't set at all.
On the other hand, the SW checks if there is some data in RX FIFO using "RXFE RX FIFO Empty" flag, which is always SET(implies no data).

Please note, I am doing these changes from userspace after adding my enhancements to BCM2835 Library form

I would like to know if some one has already realized SPI slave in RPi either from userland or kernel level using BSC /SPI slave interface.

Any ideas to test the RPis communication over SPI are welcomed.

Clarifications on BSC slave

Posted: Sun Sep 20, 2015 10:57 am
by pxcorp
I also trying to get BSC slave work (but for I2C mode) on RPi 2 (but peripherials should be same as in old BCM2835).
Yesterday I done some testing with it (via register access from userspace code) and I can get BSC slave only half working.
I can't get it working in I2C at all (it neither ack it's address, precisely doesn't ack any address), but in SPI mode it is possible to get received data.
I am not sure if receiver works correctly (I use I2C bus master as data and clock source, so I don't know exactly which bits are shifted in each clock cycle. For first tests data itself doesn't matter, in fact only clock is needed to verify that something is actualy shift to FIFO), but it at least fill FIFO with some data and with zeroes if data input is disconnected.
Also flags (in Hi DR or FR and RIS) looks to behave correct for receive.
But I cannot get transmitter working - I am able to write to TX FIFO (and see on flags that some data is actually in FIFO) but cannot get the BSC slave to shift them out.
Also setting BRK in CR doesn't clear TX FIFO - only way to clear FIFO I found is repeatively enable and disable BSC slave, as on each enable in SPI mode one byte is pulled from FIFO.
I also found that data input pin for BSC slave is marked as MISO (GPIO20) not MOSI as it should be. I cannot verify if data output is located on MOSI because I cannot get transmitter working.

I don't know if I doing something wrong when accessing peripherial or misunderstand register description or there is something in BSC slave that is not in documentation.

So I have one question for technicians in RPi foundation - isn't there any clocks that have to be enabled (and isn't by default) to get BSC slave working ? As clock distribution system in BCM is quite not public documented I cannot check this myself.

With best regards,

Re: Clarifications on BSC slave

Posted: Thu Oct 08, 2015 4:12 pm
by spotofleopard
I am struggling with SPI slave mode too.
Yesterday I got it almost working, I could receive interrupts when data is received, but the data were not completely right. Then today when I am ready to dig deeper, I can not even get the interrupts now :evil:
I am following this example:
I verified the waveforms on scope, they look perfect to me. I tied CS_N to ground.
GPIO pins are configured properly as far as I can tell.

did I miss anything?

Re: Clarifications on BSC slave

Posted: Tue Oct 27, 2015 8:38 pm
by jbeale
spotofleopard wrote: I tied CS_N to ground.
Is it possible that some state machine inside the BCM hardware needs to see a high-to-low transition on CS_N for setup before data is received? Which doesn't happen if CS_N is always low since the SPI module is first configured? (I've seen this on some other SPI chips, I haven't looked at RPi myself).

Re: Clarifications on BSC slave

Posted: Fri Aug 19, 2016 8:51 am
by baantonia
Sorry for dragging up an old thread but did anyone manage to get to the bottom of the BCM2835 SPI slave?

I can receive and process RX data but the TX FIFO fills up and never empties and I have no signal transitions on GPIO18 showing any output using an oscilloscope.