Missing EDID File and Proper Modeline Generation

[mbt28]

Hi,

I have an LVDS LCD which is connected via TIs DVI to LVDS bridge to my RPI. I have LCD datasheet however EDID port of the LCD is not working. I couldnt generate the proper modeline, could you please suggest me some source that I can learn how to calculate it properly?

Dahasheet has attahced timing table. However there is no data for vertical and horizontal blankings.
Modeline "1366x768" 78.15 1366 NA NA 1624 768 NA NA 802 -hsync -vsync
Thanks

[cleverca22]

it looks like it has an active area of 1366x768
but it wants a total of 1624x802 worth of data/timing
so you need h-backporch+hsync+h-frontporch to total up to 258 (1624-1366)

and vback+vsync+vfront needs to total to 34

its not clear how long hsync/vsync should be, you may need to just guess and experiment

and then for deciding how to allocate the remaining between front and back porch, just guess, and see how the image appears on the screen

the backporch i believe is how much time is between the syncpulse, and the active display area, so a larger backporch will shift the image down or left

i'm more familiar with how DPI then accepts all of those params, so i'm not sure how you would then encode those into the DSI config

Code: Select all

> 1624*802*60
78146880

and to get 60fps at the desired resolution, you then need a pixel clock of 78,146,880hz