rlatinov
Posts: 20
Joined: Mon Jun 26, 2017 7:35 pm

[SOLVED] Pi 3 B+ Core Mailboxes

Mon Mar 26, 2018 11:42 pm

Hello,

I am working for Marquette University in the U.S. I am currently experimenting with the new Pi 3 B+ boards for multi core capabilities in a bare metal environment. I had code that worked on the previous Pi 3 B (non +) model, which uses the BCM2837 SoC, compared to the new BCM2837B0 SoC on the B+.

The code that I have working on the Pi 3 B model use the core mailboxes to unpark the cores to a certain address. The mailbox addresses I used are 0x4000008C, 0x4000009C, 0x400000AC, and 0x400000BC for the core 0, 1, 2, and 3 mailboxes, respectively. These addresses work for the Pi 3 B, but they do not work for the Pi 3 B+.

If there is anyone who knows the core mailboxes for the 3 B+, or any related information, I would appreciate the assistance.

Thank you.

PhilE
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 1734
Joined: Mon Sep 29, 2014 1:07 pm
Location: Cambridge

Re: Pi 3 B+ Core Mailboxes

Tue Mar 27, 2018 7:16 am

None of the peripherals have changed between A0 and B0, so the problem must be elsewhere. If you post your code I may be able to spot the problem.

rlatinov
Posts: 20
Joined: Mon Jun 26, 2017 7:35 pm

Re: Pi 3 B+ Core Mailboxes

Tue Mar 27, 2018 4:03 pm

Here is the code I have in different files:

unparkcore.c

Code: Select all

extern void CoreSetup(void) __attribute__((naked));
typedef void (*fn)(void);

void printcpsr(void);

/* array to hold the initial stack pointer address for each core */
unsigned int core_init_sp[4];

/* array for holding the address of the starting point for each core */
void *corestart[4];

void unparkcore(int num, void *procaddr) {
    /* parameter checking */
    if (num > 0 && num < 4)
    {
        corestart[num] = (void *) procaddr;
        *(volatile fn *)(CORE_MBOX_BASE + CORE_MBOX_OFFSET * num) = CoreSetup;
    }
}

CoreSetup.S

Code: Select all

.globl CoreSetup
CoreSetup:
    /* change processor to SYSTEM mode */
    mrs     r0, cpsr
    orr     r0, r0, #ARM_MODE_SYS
    msr     spsr_cxsf, r0
    add     r0, pc, #4
    msr     ELR_hyp, r0
    eret

    /* get CPUID from MPIDR register and put value in r0 */
    mrc     p15, 0, r0, c0, c0, 5       /* MPIDR */
    and     r0, r0, #7                  /* last 3 bits is CPUID */

    /* multiply the CPUID by 4 to get the correct index for the arrays */
    mov     r1, r0
    mov     r2, #4
    mul     r1, r1, r2

    /* core_init_sp array is for the initial stack pointer for each core */
    ldr     r2, =core_init_sp
    ldr     sp, [r2, r1]

    /* move value to non-volatile registers before calling start_mmu */
    mov     r4, r1

    /* call start_mmu so the programmer does not have to manual call it each time they unpark a core            */
    mov     r0, #MMUTABLEBASE       /* MMUTABLEBASE from mmu.h */
    bl      start_mmu

    /* corestart array of addresses for the instruction for each core to execute once setup is done */
    ldr     r2, =corestart
    ldr     pc, [r2, r4]

#define's

Code: Select all

#define CORE_MBOX_BASE      0x4000008C
#define CORE_MBOX_OFFSET    0x10
#define MMUTABLEBASE        0x00004000

Like I said, this code works on the Pi 3 B but not on the 3 B+, which is very odd to me.

PhilE
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 1734
Joined: Mon Sep 29, 2014 1:07 pm
Location: Cambridge

Re: Pi 3 B+ Core Mailboxes

Tue Mar 27, 2018 4:25 pm

That looks sensible (no surprise, since you had it working on the 3B).

Are you saying that taking the working SD card from the 3B and putting it in the 3B+ boots core 0 but not cores 1 to 3?

FYI, the source code to the "stub" (very first instructions) for the 3B (and 3B+) is in the tools repo - armstub7.S is the 32-bit stub, armstub8.S is for 64-bit mode.

Ah, I think I know what the problem is - rather than spinning the secondary cores reading the mailboxes, which is bad for power and bus bandwidth, since May 2017 they've called "wev" (wait for event) within the polling loop. Your wakeup function needs to include an "sev" (send event) - __sev() on some compilers, or roll your own using the gcc inline assembler mechanism. I think if you try your current image on a 3B it will fail in the same way.

rlatinov
Posts: 20
Joined: Mon Jun 26, 2017 7:35 pm

Re: Pi 3 B+ Core Mailboxes

Tue Mar 27, 2018 6:19 pm

Yes, that is what was happening. When I would take the SD card from the 3B and put it into the 3B+ it would boot core 0 but not 1-3.

I tried out the sev method and that ended up working great!
Thank you!

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