PhilE
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 1907
Joined: Mon Sep 29, 2014 1:07 pm
Location: Cambridge

Re: I2S clocks, GPCLK0

Mon Oct 23, 2017 8:18 am

The Pi doesn't need MCLK - it isn't doing any kind of oversampling, etc. It has it's own sufficiently high (but unsynchronised) clocks to be able to run any additional processing - LRCK and SCLK are enough to allow it to sample (or generate) the bit data.

czyskows
Posts: 40
Joined: Sun Oct 07, 2012 5:42 am

Re: I2S clocks, GPCLK0

Mon Oct 23, 2017 8:22 am

I'm sorry, but I'm still confused - does the Pi need BCLK and LRCK from the FPGA, or will it supply its own based on set_sysclk?

PhilE
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 1907
Joined: Mon Sep 29, 2014 1:07 pm
Location: Cambridge

Re: I2S clocks, GPCLK0

Mon Oct 23, 2017 8:25 am

With the external clock generation you don't need the GPCLK or set_sysclk - the Pi syncs to LRCK and SCLK as a slave. In addition to LRCK and SCLK, the codec also needs MCLK.

HiassofT
Posts: 134
Joined: Fri Jun 30, 2017 10:07 pm

Re: I2S clocks, GPCLK0

Tue Oct 24, 2017 7:53 am

Phil's explanation is correct, here's how the I2S and clock signals wiring will look like:

FPGA is the clock master and provides the following clock outputs:

- a single BCLK output, this is connected to both RPI and codec BCLK inputs.
- a MCLK output to the codec
- a LRCLK_RPI output to the RPi
- a LRCLK_CODEC output to the codec

FPGA has 2 clock inputs from the 45/49MHz oscillators

FPGA has a bunch of control inputs for rate control, 45/49MHz selection and I2S clock enable/disable. These are connected to RPi GPIOs.

In addition to that we wire the I2S data signals directly from RPi to codec:
- RPi I2S data out is connected to codec I2S data in
- RPi I2S data in is connected to codec I2S data out

so long,

Hias

czyskows
Posts: 40
Joined: Sun Oct 07, 2012 5:42 am

Re: I2S clocks, GPCLK0

Tue Oct 24, 2017 8:32 am

Thanks, Hias! That really clarifies things. I'll finish the board layout soon and send them to be printed. Then I'll get to work on the drivers.

Cheers

HiassofT
Posts: 134
Joined: Fri Jun 30, 2017 10:07 pm

Re: I2S clocks, GPCLK0

Tue Oct 24, 2017 12:10 pm

I forgot to add one important thing:

During development it might be better to provide separate BCLK outputs (one for RPi, one for codec) on the FPGA.

Not sure if that'll actually be needed, but if during testing you find out that you eg should start codec BCLK before RPi BCLK you can simply handle that in the FPGA logic.

Driving 2 outputs of an FPGA with the same signal is easy, ripping up traces and re-routing wires on a board not so much :)

so long,

Hias

hubermat
Posts: 1
Joined: Thu Mar 29, 2018 4:00 pm

Re: I2S clocks, GPCLK0

Thu Mar 29, 2018 4:04 pm

czyskows wrote:
Tue Oct 24, 2017 8:32 am
I'll finish the board layout soon and send them to be printed. Then I'll get to work on the drivers.
Hi Czyskows,

I currently plan to create a similar setup to yours, so I wonder if you could maybe share your design/configuration of the clock generation? Did you manage to create the clocks with a CPLD?

Best regards,
hubermat

mbt28
Posts: 26
Joined: Wed Feb 04, 2015 10:35 am

Re: I2S clocks, GPCLK0

Fri May 04, 2018 2:03 pm

HiassofT wrote:
Tue Oct 24, 2017 7:53 am
Phil's explanation is correct, here's how the I2S and clock signals wiring will look like:

FPGA is the clock master and provides the following clock outputs:

- a single BCLK output, this is connected to both RPI and codec BCLK inputs.
- a MCLK output to the codec
- a LRCLK_RPI output to the RPi
- a LRCLK_CODEC output to the codec

FPGA has 2 clock inputs from the 45/49MHz oscillators

FPGA has a bunch of control inputs for rate control, 45/49MHz selection and I2S clock enable/disable. These are connected to RPi GPIOs.

In addition to that we wire the I2S data signals directly from RPi to codec:
- RPi I2S data out is connected to codec I2S data in
- RPi I2S data in is connected to codec I2S data out

so long,

Hias
Hi,

I am just curious even if create this kind of interface, how we will be sure about channel sync?

Thanks

PhilE
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 1907
Joined: Mon Sep 29, 2014 1:07 pm
Location: Cambridge

Re: I2S clocks, GPCLK0

Fri May 04, 2018 3:01 pm

I'm not sure I've understood your question, but LRCK provides the left/right sync, and the change indicates the beginning of each channel. We have to trust that the software layers and DMA engine haven't swapped the channels somewhere down the line.

mbt28
Posts: 26
Joined: Wed Feb 04, 2015 10:35 am

Re: I2S clocks, GPCLK0

Sun May 06, 2018 5:24 pm

PhilE wrote:
Fri May 04, 2018 3:01 pm
I'm not sure I've understood your question, but LRCK provides the left/right sync, and the change indicates the beginning of each channel. We have to trust that the software layers and DMA engine haven't swapped the channels somewhere down the line.
Hi,

I just meant we are sending 2 samples in each lrck but how we will be sure that we are sending correct channels from the beginning? Lets say there are 6 channels how are we sure that we are sending 1,2 and 3,4 and 5,6 in correct order?

Thanks

PhilE
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 1907
Joined: Mon Sep 29, 2014 1:07 pm
Location: Cambridge

Re: I2S clocks, GPCLK0

Sun May 06, 2018 7:14 pm

I don't think you can - all your channels have to fit into one frame if you care about synchronisation. This means making the frames larger and packing multiple samples into each half. The AudioInjector Octo card manages to multiplex 8 channels into a single stream.

mbt28
Posts: 26
Joined: Wed Feb 04, 2015 10:35 am

Re: I2S clocks, GPCLK0

Sun May 06, 2018 7:57 pm

But raspberry still uses 2 frames per channel. So how everytime will it be sure that we have correct sync? For example fpga can start to make fake lrck to dac when raspberry pi were transferring ch 3,4, 5,6,1,2 than the channels will be completely replaced.

HiassofT
Posts: 134
Joined: Fri Jun 30, 2017 10:07 pm

Re: I2S clocks, GPCLK0

Mon May 07, 2018 1:10 pm

As there's no support in the RPi hardware you have to manage channel sync in software, by starting / stopping all relevant clocks just at the right moment.

This can probably be fragile, especially if you pause a stream which will cause bcm2835 hardware to stop transferring data in the middle of a frame. As the bcm2835-i2s platform driver is a bit independent from the other involved components (sound card / codec drivers) getting the timing right could be very tricky (maybe even impossible).

If you are interested in reliable multi-channel audio via I2S then IMHO it's better to have a look at other SOCs than bcm283x which have native support for 2-8 channel audio and TDM / DSP modes in their hardware.

so long,

Hias

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