PhilE
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 1408
Joined: Mon Sep 29, 2014 1:07 pm
Location: Cambridge

Re: I2S clocks, GPCLK0

Mon Oct 23, 2017 8:18 am

The Pi doesn't need MCLK - it isn't doing any kind of oversampling, etc. It has it's own sufficiently high (but unsynchronised) clocks to be able to run any additional processing - LRCK and SCLK are enough to allow it to sample (or generate) the bit data.

czyskows
Posts: 40
Joined: Sun Oct 07, 2012 5:42 am

Re: I2S clocks, GPCLK0

Mon Oct 23, 2017 8:22 am

I'm sorry, but I'm still confused - does the Pi need BCLK and LRCK from the FPGA, or will it supply its own based on set_sysclk?

PhilE
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 1408
Joined: Mon Sep 29, 2014 1:07 pm
Location: Cambridge

Re: I2S clocks, GPCLK0

Mon Oct 23, 2017 8:25 am

With the external clock generation you don't need the GPCLK or set_sysclk - the Pi syncs to LRCK and SCLK as a slave. In addition to LRCK and SCLK, the codec also needs MCLK.

HiassofT
Posts: 28
Joined: Fri Jun 30, 2017 10:07 pm

Re: I2S clocks, GPCLK0

Tue Oct 24, 2017 7:53 am

Phil's explanation is correct, here's how the I2S and clock signals wiring will look like:

FPGA is the clock master and provides the following clock outputs:

- a single BCLK output, this is connected to both RPI and codec BCLK inputs.
- a MCLK output to the codec
- a LRCLK_RPI output to the RPi
- a LRCLK_CODEC output to the codec

FPGA has 2 clock inputs from the 45/49MHz oscillators

FPGA has a bunch of control inputs for rate control, 45/49MHz selection and I2S clock enable/disable. These are connected to RPi GPIOs.

In addition to that we wire the I2S data signals directly from RPi to codec:
- RPi I2S data out is connected to codec I2S data in
- RPi I2S data in is connected to codec I2S data out

so long,

Hias

czyskows
Posts: 40
Joined: Sun Oct 07, 2012 5:42 am

Re: I2S clocks, GPCLK0

Tue Oct 24, 2017 8:32 am

Thanks, Hias! That really clarifies things. I'll finish the board layout soon and send them to be printed. Then I'll get to work on the drivers.

Cheers

HiassofT
Posts: 28
Joined: Fri Jun 30, 2017 10:07 pm

Re: I2S clocks, GPCLK0

Tue Oct 24, 2017 12:10 pm

I forgot to add one important thing:

During development it might be better to provide separate BCLK outputs (one for RPi, one for codec) on the FPGA.

Not sure if that'll actually be needed, but if during testing you find out that you eg should start codec BCLK before RPi BCLK you can simply handle that in the FPGA logic.

Driving 2 outputs of an FPGA with the same signal is easy, ripping up traces and re-routing wires on a board not so much :)

so long,

Hias

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