elahav
Posts: 14
Joined: Fri Jan 18, 2019 11:08 am

PCIe node in the DTB

Sun Sep 08, 2019 6:05 pm

Is the PCIe node in the Pi4B dtb complete and accurate? It seems very terse (note that this listing was produced by running dtc on the shipped binary blob):

Code: Select all

		[email protected] {
			reg = <0x0 0x7d500000 0x9310 0x0 0x7e00f300 0x20>;
			msi-controller;
			msi-parent = <0x22>;
			#address-cells = <0x3>;
			#interrupt-cells = <0x1>;
			#size-cells = <0x2>;
			bus-range = <0x0 0x1>;
			compatible = "brcm,bcm7211-pcie", "brcm,bcm7445-pcie", "brcm,pci-plat-dev";
			max-link-speed = <0x2>;
			tot-num-pcie = <0x1>;
			linux,pci-domain = <0x0>;
			interrupts = <0x0 0x94 0x4 0x0 0x94 0x4>;
			interrupt-names = "pcie", "msi";
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x8f 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x90 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x91 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x92 0x4>;
			ranges = <0x2000000 0x0 0xf8000000 0x6 0x0 0x0 0x4000000>;
			dma-ranges = <0x2000000 0x0 0x0 0x0 0x0 0x1 0x0>;
			status = "okay";
			phandle = <0x22>;
		};
There are not entries with 'device_type="pci"', and there is only one range of addresses (memory, non-prefetchable). Also, The CPU address seems quite high (0x600000000).

PhilE
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 2302
Joined: Mon Sep 29, 2014 1:07 pm
Location: Cambridge

Re: PCIe node in the DTB

Sun Sep 08, 2019 6:09 pm

The PCIe node is correct enough to work. If somebody wants to submit corrections then I'll consider them, otherwise I won't be making any changes there.

elahav
Posts: 14
Joined: Fri Jan 18, 2019 11:08 am

Re: PCIe node in the DTB

Tue Sep 10, 2019 12:06 pm

Thanks, PhilE. But then what is the (ARM) ECAM address? For 0x7exxxxxx bus addresses I can see that the corresponding 0xfexxxxxx ARM addresses work as expected. But if PCIe is at 0x7d500000, does that mean that the ARM address is 0xfd500000? Mapping and reading from this address results in an asynchronous exception.
And is the size really 0x9310? Should it not be a multiple of 4K and cover at least the two buses?

PhilE
Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 2302
Joined: Mon Sep 29, 2014 1:07 pm
Location: Cambridge

Re: PCIe node in the DTB

Tue Sep 10, 2019 12:25 pm

I have not seen any mention of ECAM - just the 4KB steerable configuration space window at offset 0x8000 from the base address. 0x9310 is the size of the known registers, some of which are after the window (hence the odd size).

elahav
Posts: 14
Joined: Fri Jan 18, 2019 11:08 am

Re: PCIe node in the DTB

Tue Sep 10, 2019 8:30 pm

Thanks again. So I assume that the inability to read from this memory has to do with power/clocks. The Linux driver (which I think you wrote, based on the commit log...) is looking for a clock called "sw_pcie". I can't find that in the device tree.

elahav
Posts: 14
Joined: Fri Jan 18, 2019 11:08 am

Re: PCIe node in the DTB

Thu Sep 12, 2019 12:06 am

So it's not just me. I booted Linux on the device and see the following output:

Code: Select all

[    0.238668] brcm-pcie fd500000.pcie: dmabounce: initialised - 32768 kB, threshold 0x00000000c0000000
[    0.238712] brcm-pcie fd500000.pcie: could not get clock
[    0.238785] brcm-pcie fd500000.pcie: host bridge /scb/[email protected] ranges:
[    0.238836] brcm-pcie fd500000.pcie:   MEM 0x600000000..0x603ffffff -> 0xf8000000
[    0.291572] brcm-pcie fd500000.pcie: link up, 5.0 Gbps x1 (!SSC)
[    0.291855] brcm-pcie fd500000.pcie: PCI host bridge to bus 0000:00
The clock node is indeed not found, but apparently Linux can get PCIe to work without it.

Return to “Device Tree”