The USB hub+Ethernet devices on most Pis use a 24/25MHz clock from GPCLK1 via GPIO 42, so the outputs are definitely capable of generating a usable clock. The dt-blob.dts format defines a "drive_strength_mA" property for each pin - you can see it being used in the
default dt-blob source. However, the drive strength can only be set on a per-bank basis - the firmware calculates the maximum drive strength required by the pins in a bank and uses that value for the whole bank. There are 3 banks available - 0-27, 28-45 and 46-53 - and the drive strength can be set to 2, 4, 6, 8, 10, 12, 14 or 16mA; the default is 2mA.
Here's an extract of the 3B+ pin configuration:
Code: Select all
[email protected] { function = "pwm"; termination = "no_pulling"; drive_strength_mA = < 16 >; }; // Right audio
[email protected] { function = "pwm"; termination = "no_pulling"; drive_strength_mA = < 16 >; }; // Left audio
[email protected] { function = "gp_clk"; termination = "pull_down"; }; // ETH_CLK - Ethernet 25MHz output
[email protected] { function = "gp_clk"; termination = "pull_down"; }; // WIFI_CLK - Wifi 32kHz output
You'll see that no drive strength is not set for ETH_CLK or WIFI_CLK, but both inherit the 16mA setting specified for the PWM pins in the same bank; you may find you can manage with less.