GPCLK1 at GPIO42

[inac]

Hello all,

We have a CM3 and try to enable the GPCLK1 at pin 42 with the 19.2MHz clock (or something else at > 16MHz).

In the config.txt I set the GPIO mux at ALT0 (GPCLK1)

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gpio=42=a0

But the output stays low. Probably the clock source is not set right.

1) How can I set the clock source for GPCLK1 at 19.2MHz?
2) Is this pin shared with e.g. ETH can that cause problems?

Or maybe I missed some other things?

Kind regards

[PhilE]

Sorry I missed this one earlier.

Although the gpio directive will map the GPCLK1 function onto GPIO 42, it won't configure or start the clock. There isn't currently a way to do that in config.txt, so you have to fall back to using a custom dt-blob.bin - described here.

[inac]

Nice to know. Is there more documentation about the configuration of the clock?

I added

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     clock_setup 
     {
        [email protected] { freq = <19200000>; }; // Camera clock
     }; // clock_setup

That gives a clock but it's far from a nice block wave (but triangular). E.g. I see in https://pinout.xyz/pinout/gpclk# different clock sources but no idea how to set them via the dt-blob.dts. I also see things as

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clock_routing {
   ...
   [email protected] { pll = "PLLA"; chan = "APER"; };
};

But how to set the fixed 19.2 clock at the output without PLL?

- Is there a way to set the e.g. output driver strength to get a better clock (block wave)?
- How to set the clock source?

I need a clock (fixed frequency somewhere between 15Mhz - 25MHz) of a block wave.

[PhilE]

The USB hub+Ethernet devices on most Pis use a 24/25MHz clock from GPCLK1 via GPIO 42, so the outputs are definitely capable of generating a usable clock. The dt-blob.dts format defines a "drive_strength_mA" property for each pin - you can see it being used in the default dt-blob source. However, the drive strength can only be set on a per-bank basis - the firmware calculates the maximum drive strength required by the pins in a bank and uses that value for the whole bank. There are 3 banks available - 0-27, 28-45 and 46-53 - and the drive strength can be set to 2, 4, 6, 8, 10, 12, 14 or 16mA; the default is 2mA.

Here's an extract of the 3B+ pin configuration:

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            [email protected] { function = "pwm";    termination = "no_pulling"; drive_strength_mA = < 16 >; }; // Right audio
            [email protected] { function = "pwm";    termination = "no_pulling"; drive_strength_mA = < 16 >; }; // Left audio
            [email protected] { function = "gp_clk"; termination = "pull_down"; }; // ETH_CLK - Ethernet 25MHz output
            [email protected] { function = "gp_clk"; termination = "pull_down"; }; // WIFI_CLK - Wifi 32kHz output

You'll see that no drive strength is not set for ETH_CLK or WIFI_CLK, but both inherit the 16mA setting specified for the PWM pins in the same bank; you may find you can manage with less.