Perfect Martin and thanks for the info, I have already ordered a couple of RPI2 so I should get them next week (due to Easter). I will see how far I can get on the RPI1 as my primary limitation will be my skills within kernel drivers ... this is stille new territory for me but the complexity of the ...

Hey Martin, this was my idea to interrupt on the CS -> LOW from the FPGA/ASIC and poll out the data. Yes MCU utilisation will be high during this event but it is also critical to get all data as there is no resend possibility. Second option would be to implement at hardware buffer (SPI storage) or a...

Update ... :) I successfully got the ASIC/FPGA working and now are the results. I can drive the FPGA in 2 modes slave or master. 1. In slave mode the RPI can follow and I see only weird behavior of the clock (I set it to 4Mhz but in reality I see 3.4Mhz). Any thoughts on this ... I seem to have read...

Thx notro, crucial for sure, but likely not impossible I will start by writing the code under userspace and get it stable then I will have to find a way of getting it into a kernel module. Should get the ASIC/FPGA module on monday but I already have sufficient data for 1 week of coding

Hey notro, This is perfect and thanks for the great work also ... you and Martin have done a huge job on this. I should not do much USB work at the same time so this might be perfect. What is best the driver update or the Kernel update? Or will it be the same. Can I use the Mike McCauley package or ...

Hi Martin

First of all great work and huge achivement! I will be testing some ASIC / FPGA in the coming week(s). I believe I need 3-4Mbit/s over SPI DMA. Any concerns?

Best Jesper