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by czyskows
Sun Dec 03, 2017 5:20 am
Forum: Troubleshooting
Topic: GPIO not going all the way LOW [solved]
Replies: 17
Views: 3576

Re: GPIO not going all the way LOW

So, turns out I'm an idiot - and not that good at paying attention to details. I did in fact wire the voltage translator incorrectly. Guess I'm getting new boards printed. ; )

Image
by czyskows
Sat Dec 02, 2017 5:53 am
Forum: Troubleshooting
Topic: GPIO not going all the way LOW [solved]
Replies: 17
Views: 3576

Re: GPIO not going all the way LOW

It appears that GPIO16 is getting some amount of voltage from GPIO15, though I don't know why this is happening. It seems like I can still use the board if I set 15 and 16 to the same settings all the time, which is possible since they can be attached to different sides of the dual h-bridge. Thank y...
by czyskows
Thu Nov 30, 2017 4:34 pm
Forum: Troubleshooting
Topic: GPIO not going all the way LOW [solved]
Replies: 17
Views: 3576

Re: GPIO not going all the way LOW

I'm using a voltmeter on the pins.
by czyskows
Thu Nov 30, 2017 1:06 am
Forum: Troubleshooting
Topic: GPIO not going all the way LOW [solved]
Replies: 17
Views: 3576

Re: GPIO not going all the way LOW

Image

You can see where GPIO16 goes straight into the voltage translator. It's a fairly standard TI Bidirectional voltage translator commonly used on motor capes. I can't see any reason that it would be pulled high.
by czyskows
Tue Nov 28, 2017 7:33 am
Forum: Troubleshooting
Topic: GPIO not going all the way LOW [solved]
Replies: 17
Views: 3576

Re: GPIO not going all the way LOW

I was thinking that was a possibility, but it's connected to a voltage translator that merely reads the voltage then sends a different voltage to a motor driver. That also wouldn't explain why it works fine when I run Python in the console but doesn't work when I run the script.
by czyskows
Mon Nov 27, 2017 5:21 am
Forum: Troubleshooting
Topic: GPIO not going all the way LOW [solved]
Replies: 17
Views: 3576

GPIO not going all the way LOW [solved]

I'm controlling several GPIO pins with a Python script. import RPi.GPIO as GPIO import time from LS7366r import LS7366R from time import sleep encoder = LS7366R(1, 1000000, 4) GPIO.setmode(GPIO.BOARD) GPIO.setwarnings(False) ##### setup RPi GPIO pins GPIO.setup(12, GPIO.OUT) #PWM_A GPIO.setup(33, GP...
by czyskows
Tue Oct 24, 2017 8:32 am
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

Thanks, Hias! That really clarifies things. I'll finish the board layout soon and send them to be printed. Then I'll get to work on the drivers.

Cheers
by czyskows
Mon Oct 23, 2017 8:22 am
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

I'm sorry, but I'm still confused - does the Pi need BCLK and LRCK from the FPGA, or will it supply its own based on set_sysclk?
by czyskows
Mon Oct 23, 2017 8:02 am
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

So, instead, I should not have MCLK going to the Pi, but the Pi should know the frequency of the MCLK through set_sysclk? Then the Pi would get BCLK and LRCK, and the codec would get BCLK, LRCK, and MCLK?
by czyskows
Mon Oct 23, 2017 7:57 am
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

This then brings us back to the issue of the master/slave setup, since my codec has to be in slave mode to use TDM. Can the Pi be master and still receive BCLK and LRCK? The Octo has the CPU as CBM/CFM. I assume I should do the same?
by czyskows
Mon Oct 23, 2017 7:49 am
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

Hi Hias, I've been working on redesigning my board with the FPGA and external clocks, but before I get too far, I just wanted to clarify some things. My (limited) understanding is that the basic flow should look something like this: https://i.imgur.com/pioKObl.png So, the two clocks would go to the ...
by czyskows
Wed Oct 18, 2017 6:25 pm
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

Hi Hias, Thanks again. While this is frustrating, since I already designed and built another board :( I guess that's the route I have to take. I'll start making the changes to my board layout and figuring out the FPGA programming now. I'm sure I'll be back with more questions once the hardware side ...
by czyskows
Mon Oct 16, 2017 6:33 pm
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

Hi Hias, First, I can't thank you enough for your patience and your willingness to help with this. Most of this is pretty far over my head and I'd be even more lost if it weren't for yours and Phil's direction. Second, What I'm understanding now is that, with the current hardware setup, i.e. getting...
by czyskows
Mon Oct 16, 2017 2:41 am
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

Hi, I tried implementing the 8-channel conversion with sox, but I'm still getting output out of only 2 channels. My process was: sox MultOut.wav MultOut.raw sox --bits 32 --endian little --channels 2 --rate 176400 MultOut.raw MultOut.wav The codec setup that I have is still the same as I had before:...
by czyskows
Mon Oct 09, 2017 9:14 pm
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

I'm sorry, but I'm still trying to clarify exactly what you're describing. My understanding is that I need an alsa plugin that will do automatic sample rate conversion to 4Fs over 2 channels. Is this correct? The only sample rate conversion plugins I've been able to find are static, e.g. ones that w...
by czyskows
Sun Oct 08, 2017 10:37 pm
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

Hi. I took your suggestion and started over with the rpi-dac driver as a model. I now have stereo audio sounding great! I'm still confused as to the multichannel parts, though. I'm setting the TDM slots as you said, and I'm setting the DSP_A dai_fmt. with those settings, I'm getting perfect audio, b...
by czyskows
Fri Oct 06, 2017 7:32 pm
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

Thanks for this, Hias. This is a big help. My initial thinking was that it made sense to use the Octo driver as a template since that was so close to what I wanted to do, but I can see now that what you're suggesting makes more sense. I'll get started on reworking the driver now. I'm sure I'll have ...
by czyskows
Fri Oct 06, 2017 6:32 am
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

Hi Phil, Here are my clocks: https://imgur.com/Tx4qVnI.png https://imgur.com/qyqLhr1.png Sorry - my digital scope only has two channels and photos of my analog scope probably aren't helpful. The top image shows MCLK in yellow and BCLK in cyan. The second image has LRCK in yellow and BCLK in cyan. Th...
by czyskows
Thu Oct 05, 2017 5:04 pm
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

Yes, I will do this tonight when I get home from work. Thanks! One thing that occurs to me - I'm setting the clock rate in the cs42xx8.c driver in the probe function: cs42xx8->clk = devm_clk_get(dev, "mclk"); if (IS_ERR(cs42xx8->clk)) { dev_err(dev, "failed to get the clock: %ld\n", PTR_ERR(cs42xx8-...
by czyskows
Thu Oct 05, 2017 4:38 pm
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

Hi, and thanks again. Is there really no way to have the cpu in CBM/CFM and have this work? I can't believe it is impossible to drive the CS42448 with one of the RPI's clocks and make it work. I'm still baffled as to why I get proper clock signals when both cpu and Codec are in slave mode, but still...
by czyskows
Wed Oct 04, 2017 11:19 pm
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

Thanks, Hias, I do have the MCLK running at 256XFS - 11.289600 = 44.1K * 256. As for the CS42448 driving the BCLK - How is this done if the CS42448 is the slave? My understanding was that the master provides the clocks to which the slave syncs. The issues are still: 1. Why I get no LRCK or BCLK when...
by czyskows
Wed Oct 04, 2017 4:35 pm
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

What's driving me absolutely crazy, though, is that when both CPU and codec are in CBS/CFS mode, I get the right clocks - 11.2896MHz for MCLK and BCLK, and 44.1K for LRCK - but then the audio plays at 1/4 speed. This lead me to believe that somehow the TDM format wasn't being set on the codec proper...
by czyskows
Wed Oct 04, 2017 12:52 am
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

Hi again, So it seems like I'm still having an issue. As I mentioned above, I was designating both the codec and the CPU as CBS and CFS: // set codec DAI configuration int ret = snd_soc_dai_set_fmt(rtd->codec_dai, SND_SOC_DAIFMT_CBS_CFS|SND_SOC_DAIFMT_DSP_A| SND_SOC_DAIFMT_NB_NF); if (ret < 0) retur...
by czyskows
Fri Sep 29, 2017 3:07 am
Forum: Device Tree
Topic: I2S clocks, GPCLK0
Replies: 62
Views: 17463

Re: I2S clocks, GPCLK0

Clocks are looking good! The codec (cs42448) actually needs to be in slave mode to operate in TDM mode, so my FMT settings are: // set codec DAI configuration int ret = snd_soc_dai_set_fmt(rtd->codec_dai, SND_SOC_DAIFMT_CBS_CFS|SND_SOC_DAIFMT_DSP_A| SND_SOC_DAIFMT_NB_NF); if (ret < 0) return ret; //...

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