Go to advanced search

by justinvoss
Wed Jun 12, 2019 7:32 pm
Forum: Bare metal, Assembly language
Topic: Changing TTBR1_EL1 while memory caching enabled?
Replies: 5
Views: 561

Re: Changing TTBR1_EL1 while memory caching enabled?

I think I solved it! The trick was revealed by this sentence in the ARM Programmer's Guide: The attributes specified in the TCR_EL1 must be the same as those specified for the virtual memory region in which the translation tables are stored. Caching the translation tables is the normal default behav...
by justinvoss
Wed Jun 12, 2019 1:57 am
Forum: Bare metal, Assembly language
Topic: Changing TTBR1_EL1 while memory caching enabled?
Replies: 5
Views: 561

Re: Changing TTBR1_EL1 while memory caching enabled?

As for table the TTBR1_EL1 is the easy one because usually you have the 1:1 mapping on TTBR0_EL1 so you can just initially use a top level table all zeroed and try bringing it online. You don't actually need a table in the virtual space at all until you want to setup a virtual block, and typically ...
by justinvoss
Tue Jun 11, 2019 10:02 pm
Forum: Bare metal, Assembly language
Topic: Changing TTBR1_EL1 while memory caching enabled?
Replies: 5
Views: 561

Changing TTBR1_EL1 while memory caching enabled?

I'm working on writing a kernel for my Raspberry Pi 3 (Model B), and things are going fairly well, except that I cannot figure out how to swap the TTBR1_EL1 register without causing an exception when memory caching is enabled. Here's my setup: My kernel is an ELF file, which expects to be loaded in ...

Go to advanced search