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by xStSx
Sun Dec 30, 2018 7:57 am
Forum: Interfacing (DSI, CSI, I2C, etc.)
Topic: STICKY: The I2S sound thread.
Replies: 885
Views: 416804

Re: STICKY: The I2S sound thread.

How did you measure the frequencies? The 48kHz measurement shows a deviation of approx 40ppm which is about to be expected. A 3.072MHz bclk will be derived from the 500MHz PLL by using a fractional divider. Average frequency should be pretty spot on, but you may see a 2ns jitter when using a rather...
by xStSx
Sat Dec 22, 2018 4:56 pm
Forum: Interfacing (DSI, CSI, I2C, etc.)
Topic: STICKY: The I2S sound thread.
Replies: 885
Views: 416804

Re: STICKY: The I2S sound thread.

If you expereience "data shifts by one bit" you are probably using the wrong mode. In I2S mode the MSB is transmitted 1 cycle after the LRCLK change, in left-justified mode it's transmitted immediately after the LRCLK change. You are right.. It's a specification of protocol. My bad. And actually no...
by xStSx
Tue Dec 18, 2018 11:46 am
Forum: Interfacing (DSI, CSI, I2C, etc.)
Topic: STICKY: The I2S sound thread.
Replies: 885
Views: 416804

Re: STICKY: The I2S sound thread.

Hi, I have 2 questions, maybe a solution is pretty simple... but I got lost a little bit in all dts stuff. Any way I got I2S working in/out 24bit,48KHz. But.. 1) Is there any way make bclk constantly out, not only when there is some data to record/play? I just want get 3.072MHz at bclk pin constantl...

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