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by Schnoogle
Mon Jul 27, 2020 7:43 pm
Forum: Bare metal, Assembly language
Topic: PI3 - Which memory settings ensure memory coherency between ARM and VC?
Replies: 9
Views: 596

Re: PI3 - Which memory settings ensure memory coherency between ARM and VC?

Hi, the 0xffff_ffff_c00f_0000 is a virtual address. It is mapped to physical 0x000f_0000. The VC will get the physical address ored with 0xc000_0000 and results in 0xc00f_0000 that is passed to the VideoCore.
by Schnoogle
Mon Jul 27, 2020 8:25 am
Forum: Bare metal, Assembly language
Topic: PI3 - Which memory settings ensure memory coherency between ARM and VC?
Replies: 9
Views: 596

Re: PI3 - Which memory settings ensure memory coherency between ARM and VC?

Hi, thanks again for all your valuable feedback. I guess I'm quite able to picture now the theory ;) - however, practice is still driving me nuts :O So, let me share some of my code and hopefully someone is able to spot an error ;) 1. The MAIR setting is as following: /// Device Memory nGnRnE NGNRNE...
by Schnoogle
Mon Jul 27, 2020 7:49 am
Forum: Bare metal, Assembly language
Topic: Setting up exceptions made easy (??)
Replies: 5
Views: 295

Re: Setting up exceptions made easy (??)

Hi, well there is a reason that interrupt/exception handler seem complicated at first look: Any exception is interrupting the process flow on an arbitrary position where any number of registers has a specific value. If the CPU calls the exception handler it expects to find the register values after ...
by Schnoogle
Sun Jul 26, 2020 6:22 pm
Forum: Bare metal, Assembly language
Topic: PI3 - Which memory settings ensure memory coherency between ARM and VC?
Replies: 9
Views: 596

Re: PI3 - Which memory settings ensure memory coherency between ARM and VC?

Hi, thanks for your response and this already sheds some lights :) However, my current observations is as follows: The memory region shared between ARM and GPU is configured as "outer shareable" in the corresposponding translation table entry. The MAIR point to a MAIR setting of 0x44 - which is oute...
by Schnoogle
Sun Jul 26, 2020 1:21 pm
Forum: Bare metal, Assembly language
Topic: PI3 - Which memory settings ensure memory coherency between ARM and VC?
Replies: 9
Views: 596

PI3 - Which memory settings ensure memory coherency between ARM and VC?

Hi there, I'm currently a bit lost in the whole bunch of possible settings for the memory regions of the ARMv8. I try to figure out what settings are required to ensure a specific memory region shared between ARM and VideoCore is coherent. There are the general settings - like shareability in the MM...
by Schnoogle
Sun Jul 26, 2020 12:17 pm
Forum: Bare metal, Assembly language
Topic: Updating/Changing MMU Page Tables
Replies: 15
Views: 1011

Re: Updating/Changing MMU Page Tables

Well, so after I cross checked my code several times I found I had some math issues when updating the translation tables. So this part of the MMU does work now also updating TTBR1 "on-the-fly" ;) Thanks a ton for your help so far!!! The only thing which is still driving me nuts is the alignment abor...
by Schnoogle
Sat Jul 25, 2020 8:59 pm
Forum: Bare metal, Assembly language
Topic: Updating/Changing MMU Page Tables
Replies: 15
Views: 1011

Re: Updating/Changing MMU Page Tables

Hi, so I further analyzed the issues on the real hardware and interestingly an access to the virtual address 0xffffffffffee81dc leads to an Alignment Abort even though the alignment checks are disabled in sctlr1_el1 register. If I'm not using the virtual address such as 0x000e81dc then no such abort...
by Schnoogle
Sat Jul 25, 2020 2:49 pm
Forum: Bare metal, Assembly language
Topic: Emulator for directly programing RPi
Replies: 12
Views: 773

Re: Emulator for directly programing RPi

Hey, there are also some bare metal bootloader available. You put only those BL on your SD card and once the Pi is powered up you can send the kernel to test via UART or other data transfer, depending on the supported mechanics of the bootloader. This will reduce the SD card dance quite significantl...
by Schnoogle
Fri Jul 24, 2020 10:31 pm
Forum: Bare metal, Assembly language
Topic: Updating/Changing MMU Page Tables
Replies: 15
Views: 1011

Re: Updating/Changing MMU Page Tables

Hi, so my first attempts keeping TTBR0 entries stable but maintaining TTBR1 entries as they are required was quite successful running in QEMU. However, on the real hardware (Pi3) this fails and the system hangs. I guess the reason is data abort or mmu translation fault. As it is quite hard to analys...
by Schnoogle
Mon Jul 20, 2020 8:46 pm
Forum: Bare metal, Assembly language
Topic: Updating/Changing MMU Page Tables
Replies: 15
Views: 1011

Re: Updating/Changing MMU Page Tables

Hey,

thanks for the detailed response and the code example. I'll try to adopt the example given to my use case and cross fingers that it will work. ;)
May take a whyle as I need to refactor my memory allocator for this :oops:

BR and thanks for your patience
Schnoogle
by Schnoogle
Mon Jul 20, 2020 3:23 pm
Forum: Bare metal, Assembly language
Topic: Updating/Changing MMU Page Tables
Replies: 15
Views: 1011

Re: Updating/Changing MMU Page Tables

Hey thanks again for your hints. Maybe I did explain something wrong or I understood you wron so please excuse my ignorance if I did. I'm using currently ONLY TTBR0 entries covering a 1:1 mapping. I've not even setup any TTBR1 virtual mapping. Withinmy implementation I'd like to stick with my 1:1 ma...
by Schnoogle
Mon Jul 20, 2020 8:57 am
Forum: Bare metal, Assembly language
Topic: Updating/Changing MMU Page Tables
Replies: 15
Views: 1011

Re: Updating/Changing MMU Page Tables

Hey, I've found this paper: https://static.docs.arm.com/100940/0100/armv8_a_address%20translation_100940_0100_en.pdf and according to the description as far as I understood the TTBR1_EL1 entries might not help as they are only used for the "upper" virtual memory map. I'm currently only using the low...
by Schnoogle
Sun Jul 19, 2020 11:19 am
Forum: Bare metal, Assembly language
Topic: Updating/Changing MMU Page Tables
Replies: 15
Views: 1011

Re: Updating/Changing MMU Page Tables

Hi, thanks for the hints and suggestions. I'll try both things you mention. However, if it comes to maintaining the TLB entries that TTBR1_EL1 is referring to, can this also hold 1:1 mappings, so actually beeing the same values as the ones TTBR0_EL1 is referring to (not the same table but the same v...
by Schnoogle
Sat Jul 18, 2020 12:21 pm
Forum: Bare metal, Assembly language
Topic: Updating/Changing MMU Page Tables
Replies: 15
Views: 1011

Re: Updating/Changing MMU Page Tables

Hi there, I seem also to have some issues with runtime TLB maintenance (aarch64). The initial TLB configuration after booting my kernel is working fine. I'm setting 1:1 memory mapping on a 2MB block level. During runtime I treid to modify a number of pages from beeing cacheable to beeing shared and ...
by Schnoogle
Fri Jul 17, 2020 4:47 pm
Forum: Bare metal, Assembly language
Topic: RPi3 - VCHIQ help required
Replies: 0
Views: 256

RPi3 - VCHIQ help required

Hi there, I'm in the phase of implementing a VCHIQ "driver" in Rust. I was able to manage to setup the SlotZero structure and fill it with the correct data and pass its memory address via mailbox property interface to the VideoCore. This initial handshake works fine. The VC part of the VCHIQ interfa...
by Schnoogle
Thu May 28, 2020 7:50 am
Forum: Bare metal, Assembly language
Topic: xRTOS - turn off MMU and still use Semaphores?
Replies: 16
Views: 1374

Re: xRTOS - turn off MMU and still use Semaphores?

Hi, as far as I'm aware the Semaphore implementions typically uses atomic memory operations under the hood. Like the ldaxrb and stlxrb instructions. Those require the MMU to be enabled and setup to work. Otherwise those will just hang the core that tries to execute those instructions. The reason for...
by Schnoogle
Thu May 28, 2020 7:45 am
Forum: Bare metal, Assembly language
Topic: Pi3 - VCHIQ - mailbox property returns 0xffff_ffff when setting base address
Replies: 9
Views: 812

Re: Pi3 - VCHIQ - mailbox property returns 0xffff_ffff when setting base address

Thanks for your hints so far. @Ultibo: The "packed" attribute was one of my attempts to get the structures with the correct byte ordering and size, I've removed this but it did not changed the overall behavior. The DEBUG_MAX value is 11, so the SlotZero size is 1288 bytes long in total (if I remembe...
by Schnoogle
Tue May 26, 2020 8:55 am
Forum: Bare metal, Assembly language
Topic: Pi3 - VCHIQ - mailbox property returns 0xffff_ffff when setting base address
Replies: 9
Views: 812

Re: Pi3 - VCHIQ - mailbox property returns 0xffff_ffff when setting base address

I would say share everything. Otherwise we are flying blind too :) Well, yea - you are right. As my PoC code is not yet on github lets try to share as much as possible here - don't know how familiar you all are with rust yet, but the syntax should be fairly easy to understand. 1. The shared data st...
by Schnoogle
Tue May 26, 2020 7:29 am
Forum: Bare metal, Assembly language
Topic: Pi3 - VCHIQ - mailbox property returns 0xffff_ffff when setting base address
Replies: 9
Views: 812

Re: Pi3 - VCHIQ - mailbox property returns 0xffff_ffff when setting base address

Hi, thx for the hint with the cache. However, I already tried this with no much luck. Also the memory region passed to the VC is configured within the MMU to be coherent memory - so this area is not cached and outer shareable. I might share the MMU settings if relevant, but could this really be the ...
by Schnoogle
Mon May 25, 2020 9:49 pm
Forum: Bare metal, Assembly language
Topic: Pi3 - VCHIQ - mailbox property returns 0xffff_ffff when setting base address
Replies: 9
Views: 812

Re: Pi3 - VCHIQ - mailbox property returns 0xffff_ffff when setting base address

Hey, thanks for the link to the table of blinking codes ;) Crashing the VC firmware feels quite severe to me, from just setting the VCHIQ base address using the property mailbox. Would it be possible, by any chance, to get some info‘s why the VC firmware crashes when sending the VCHIQ base address? ...
by Schnoogle
Mon May 25, 2020 6:48 pm
Forum: Bare metal, Assembly language
Topic: Pi3 - VCHIQ - mailbox property returns 0xffff_ffff when setting base address
Replies: 9
Views: 812

Pi3 - VCHIQ - mailbox property returns 0xffff_ffff when setting base address

Hi there, I know I already got the VCHIQ baremetal interface up and running sometime back - however, while trying to re-implement this stuff in Rust I'm currently kinda stuck. When setting the base address of the memory region containing the VCHIQ setup data (SlotZero) I recieve 0xFFFF_FFFF as statu...
by Schnoogle
Mon May 25, 2020 2:53 pm
Forum: Bare metal, Assembly language
Topic: PI3 - Latest firmware (bootcode, start_x, fixup_x) seem to break atomic operations ...
Replies: 0
Views: 223

PI3 - Latest firmware (bootcode, start_x, fixup_x) seem to break atomic operations ...

Hi there, if recently used the latest RPi3 firmware files from this repo: https://github.com/raspberrypi/firmware/tree/master/boot namely: - bootcode.bin - start_x.elf - fixup_x.dat However, without any code changes the Pi does now hang when trying run my baremetal code. It does hang actually when w...
by Schnoogle
Sat May 16, 2020 10:28 am
Forum: Bare metal, Assembly language
Topic: RPi 3 - Is the VideoCore firmware guaranteed to be Aarch32 ?
Replies: 2
Views: 382

RPi 3 - Is the VideoCore firmware guaranteed to be Aarch32 ?

Hi there, i'm working on a bare-metal VCHIQ interface in Rust. To properl implement the same I understood that there is a huge bunch of memory area ory shared between ARM CPU and the VC GPU. As this memory layout also contains several pointer values it's important to know whether those pointers are ...
by Schnoogle
Wed Apr 22, 2020 7:24 pm
Forum: Bare metal, Assembly language
Topic: miniUART and clock freq
Replies: 6
Views: 883

Re: miniUART and clock freq

What cycles should I wait? Can I use SP804-based ARM timer for this? Well from my experince this are CPU cycles you need to wait. Regardless of the current speed. I've implemented this by the ammount of nop instrustions as cycles are requested to pass by and it works quite well. Let me share the co...

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