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by Schnoogle
Sat Jan 18, 2020 11:19 am
Forum: Bare metal, Assembly language
Topic: i2c 2 alt functions
Replies: 11
Views: 264

Re: i2c 2 alt functions

Hey, if you check the BCM2837 Peripheral document there is a table for all GPIO's and there ALT functions. Also it only talks about one I2C Master and once Slave peripheral being available. In the GPIO mapping table look for SDA0/SCL0 assignments for I2C0 and SDA1/SCL1 assignments for I2C1 on the GP...
by Schnoogle
Fri Jan 17, 2020 3:41 pm
Forum: Bare metal, Assembly language
Topic: Mini UART
Replies: 9
Views: 269

Re: Mini UART

Hm, well.... this sounds interesting. Could you maybe dump the configuration/content of the following registers after you've send a character that is not seen in your terminal:

AUX_MU_STAT_REG
AUX_MU_CNTL_REG
AUX_MU_LSR_REG
AUX_MU_IIR_REG

??
by Schnoogle
Fri Jan 17, 2020 12:38 pm
Forum: Bare metal, Assembly language
Topic: Mini UART
Replies: 9
Views: 269

Re: Mini UART

Hey, thanks for the additional insights. As the code looks good to me and as you are saying the terminal is showing the characters only after "\r\n" may I ask what terminal program you use? Maybe it relates to a setting their ? I'm using TeraTerm( https://osdn.net/projects/ttssh2/releases/ ) for win...
by Schnoogle
Fri Jan 17, 2020 11:48 am
Forum: Bare metal, Assembly language
Topic: Mini UART
Replies: 9
Views: 269

Re: Mini UART

Hey there, I'm struggling currently a bit what exactly your issue is. On the one hand hand you asking fro flushing (which is the sending part I guess) and on the other hand you provide a code snipped for reading inbound data. I've never had issues at my UART1(miniUart) that single characters did not...
by Schnoogle
Wed Jan 15, 2020 2:26 pm
Forum: Bare metal, Assembly language
Topic: AArch64: calling EL0 function from EL1
Replies: 2
Views: 122

Re: AArch64: calling EL0 function from EL1

Hi, as far as I'm aware this is not possible. The processor can only switch exception levels if an exception is raised (like an interrupt or an call to SMC, HYP, SVC) or using the ERET instruction. While ERET goes down the exceptions levels from EL3->EL2->EL1->EL0 the interrupts or system exception ...
by Schnoogle
Wed Jan 08, 2020 8:44 am
Forum: Bare metal, Assembly language
Topic: Announce: RusPiRo - a kernel the Rust way ;)
Replies: 60
Views: 7698

Re: Announce: RusPiRo - a kernel the Rust way ;)

I've found that anything over 60kB program size starts to feel slow when loading over UART at 115200 baud - so at some point there will be diminishing returns in having everything in the executable when testing on actual hardware. Well you are totally right, as the kernel size grows this might get ...
by Schnoogle
Sat Jan 04, 2020 4:49 pm
Forum: Bare metal, Assembly language
Topic: Announce: RusPiRo - a kernel the Rust way ;)
Replies: 60
Views: 7698

Re: Announce: RusPiRo - a kernel the Rust way ;)

Hey, thanks for your suggestions. If I got your references right, than there seem to be nothing required to be supported from bare-metal kernel point of view to enable JTAG debugging. https://github.com/rust-embedded/rust-raspi3-OS-tutorials/tree/master/09_hw_debug_JTAG#software-setup So you only ne...
by Schnoogle
Sun Dec 22, 2019 11:17 am
Forum: Bare metal, Assembly language
Topic: [SOLVED] AARCH64 SIMD/Floating Point Instructions Causing Exceptions
Replies: 4
Views: 504

Re: AARCH64 SIMD/Floating Point Instructions Causing Exceptions

Thank you for your help! I couldn't get the "register::cpu" crate functionality to work for some reason so used asm!() macro directly: Which crate exactly are you using here? Maybe you want to give my ruspiro-register crate a try? If you use the latest version like so: [dependencies] ruspiro-regist...
by Schnoogle
Fri Dec 20, 2019 9:29 am
Forum: Bare metal, Assembly language
Topic: Announce: RusPiRo - a kernel the Rust way ;)
Replies: 60
Views: 7698

Re: Announce: RusPiRo - a kernel the Rust way - Bootloader ready

Hi there, long time no see :) It really took me a time to get use to aarch64 on the Raspberry Pi, but now I can share that I've released a Bootloader for the RusPiRo journey. It's written mainly in Rust - the bootstrapping is assembly. The Repo can be found here: https://github.com/RusPiRo/ruspiro-l...
by Schnoogle
Fri Dec 20, 2019 8:56 am
Forum: Bare metal, Assembly language
Topic: [SOLVED] AARCH64 SIMD/Floating Point Instructions Causing Exceptions
Replies: 4
Views: 504

Re: AARCH64 SIMD/Floating Point Instructions Causing Exceptions

Hi rahealy,

as far as I'm aware in aarch64 this bit will ensure that FP/NEON instruction are not trapped (raising an exception) :

Code: Select all

mrs    x1, cpacr_el1
mov    x0, #(3 << 20)
orr    x0, x1, x0
msr    cpacr_el1, x0
BR
Schnoogle
by Schnoogle
Thu Dec 12, 2019 8:38 am
Forum: Bare metal, Assembly language
Topic: BX LR Seg Fault
Replies: 20
Views: 890

Re: BX LR Seg Fault

Hi, I'm definitely not an expert but from the code snippets you shared I assume you expect the link return address register (LR) to be "stacked". But it's not. So whenever you do a branch link call BL the contents of the LR register will be updated containing the last return address. But when you ca...
by Schnoogle
Fri Dec 06, 2019 8:39 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - EL2 switch to EL3 - Exception Handler not called
Replies: 9
Views: 715

Re: [SOLVED] Aarch64 - EL2 switch to EL3 - Exception Handler not called

Hey joncs,

thanks for the hint. This seems like a reasonable approach. I‘ll definitely give it a try... I was not aware of this possibility.

Regards
Schnoogle
by Schnoogle
Tue Dec 03, 2019 6:44 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - EL2 switch to EL3 - Exception Handler not called
Replies: 9
Views: 715

Re: Aarch64 - EL2 switch to EL3 - Exception Handler not called

Hey there, well it turned out that the default armv8stub.s does set the register SCR_EL to prevent any SMC call and makes it an undefined instruction (SMD flag set in SCR_EL3). So there seem to be only one way to deal with it using a config.txt to let my own kernel kick-off in EL3 and work from ther...
by Schnoogle
Tue Dec 03, 2019 9:49 am
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 RPi3 - MMU issue
Replies: 6
Views: 1008

Re: Aarch64 RPi3 - MMU issue

Hi Valc,

thanks for your efforts. I guess this might have been the issue. After some refactoring of my code which might have eliminated this subtle bug as well the MMU is doing fine in aarch64 mode :)
Will mark the topic as solved.
by Schnoogle
Sun Nov 24, 2019 1:45 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - EL2 switch to EL3 - Exception Handler not called
Replies: 9
Views: 715

Re: Aarch64 - EL2 switch to EL3 - Exception Handler not called

If the first thing you want to do is to jump to EL3, i believe configuring it to start in EL3 is the best. Well at the moment my kernel targets to run in EL2 and as it shall act as kind of bootloader I‘d like to use EL3 as trampoline to switch to aarch32 EL2 in case a 32bit kernel is loaded and abl...
by Schnoogle
Sun Nov 24, 2019 11:24 am
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - EL2 switch to EL3 - Exception Handler not called
Replies: 9
Views: 715

Re: Aarch64 - EL2 switch to EL3 - Exception Handler not called

Hey,

yes my Pi is booting in EL2.
So would you propose to use config.txt to boot in EL3 to achieve what I‘m trying to do?

BR
Schnoogle
by Schnoogle
Sat Nov 23, 2019 11:56 am
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - EL2 switch to EL3 - Exception Handler not called
Replies: 9
Views: 715

[SOLVED] Aarch64 - EL2 switch to EL3 - Exception Handler not called

Hi there, I'm using my baremetal Pi in aarch64 mode. As far as I'm aware the initial mode (without any config.txt) would be aarch64 in EL2, right? What I try to achieve is to switch to EL3 in aarch64 and from there return to EL2 in aarch32 mode. This whole thing is working fine in QEMU but fails on ...
by Schnoogle
Sun Nov 03, 2019 5:22 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - RPi3 - Interrupts not triggering exception handler
Replies: 2
Views: 1020

Re: Aarch64 - RPi3 - Interrupts not triggering exception handler

Hi there, well it seems that I was able to solve this on my own. I was missing to configure the IRQ routing in register HCR_EL2 . Even though my bare metal kernel keeps running in EL2 the interrups (e. from the timer) seem to be delivered only if this register is set to route any IRQ raised in any l...
by Schnoogle
Sun Nov 03, 2019 1:00 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - RPi3 - Interrupts not triggering exception handler
Replies: 2
Views: 1020

Re: Aarch64 - RPi3 - Interrupts not triggering exception handler

Hi there,

while further investigating it seemed to be the case that interrupts are only delivered after switching from EL2 to EL1 which seems a bit of a surprise to me. Is there a register I need to write to enable interrupts also being delivered when the core is running in EL2 mode?
by Schnoogle
Thu Oct 31, 2019 3:50 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 - RPi3 - Interrupts not triggering exception handler
Replies: 2
Views: 1020

[SOLVED] Aarch64 - RPi3 - Interrupts not triggering exception handler

Hi there, I'm facing some trouble with interrupt handling in AARCH64 mode. I guess I set up everything - to my knowledge - but the interrupts does not trigger an exception call from my exception vector table. However, I can see there are pending interrupts based on the pending interrupt registers. W...
by Schnoogle
Thu Oct 31, 2019 2:34 pm
Forum: Bare metal, Assembly language
Topic: Inter CPU mailboxes
Replies: 1
Views: 472

Re: Inter CPU mailboxes

Hi there, you might want to checkout this document: https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf It describes the core mailboxes available to achieve inter core communication. Those mailboxes also support interrupts to be triggered to ensure another core only...
by Schnoogle
Tue Oct 29, 2019 7:09 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 RPi3 - MMU issue
Replies: 6
Views: 1008

Re: Aarch64 RPi3 - MMU issue

I'd gladly do that, although it's really primitive (just a prove of concept that 1:1 MMU mapping works at all, because other than for checking this feature out i did not find any use for it in my code) Well actually this is all what I’m after. I need the MMU to be set up to be able to use atomic op...
by Schnoogle
Tue Oct 29, 2019 2:57 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 RPi3 - MMU issue
Replies: 6
Views: 1008

Re: Aarch64 RPi3 - MMU issue

Hi,

thx for the hint. I'll try to find my way with QEMU :)

In the meantime maybe you might be able to share the MMU entries you are using in case you also use 1:1 mapping with 2 levels only....

BR
Schnoogle
by Schnoogle
Sun Oct 27, 2019 8:59 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] Aarch64 RPi3 - MMU issue
Replies: 6
Views: 1008

[SOLVED] Aarch64 RPi3 - MMU issue

Hi there, I do have a MMU issue I do not quite understand. I've read all the great and well written posts on that topic and I guess I did understand how to set the MMU up and I did this successfully with a 1:1 mapping. However, the memory access creates an Address size fault as soon as I try to acce...
by Schnoogle
Fri Oct 25, 2019 5:21 pm
Forum: Bare metal, Assembly language
Topic: [SOLVED] QEMU - AARCH64 RPi3 - DataAbort on address > 0x4000_0000
Replies: 1
Views: 726

Re: QEMU - AARCH64 RPi3 - DataAbort on address > 0x4000_0000

Hey there,

never mind and sorry for having bothered you :oops: . I figured it out. It was a MMU issue and the data abort indicated an translation fault at level 2. Sorry for the really beginner thing but I'm quite new to QEMU ;)

BR
Schnoogle

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